[XS] Change in coreboot[main]: mb/google/brox/var/lotso: disable RTS5227 PCIE L0s support

[Jian Tong (Code Review)]

Jian Tong has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84177?usp=email )

Change subject: mb/google/brox/var/lotso: disable RTS5227 PCIE L0s support
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mb/google/brox/var/lotso: disable RTS5227 PCIE L0s support

Because of RTS5227 don't support L0s, so set to ASPM_L1.

BUG=b:359409425
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage

Change-Id: I87bb0d195566d273951dee6eeb54c9b388dd7607
Signed-off-by: Jian Tong 
---
M src/mainboard/google/brox/variants/lotso/overridetree.cb
1 file changed, 1 insertion(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/84177/1

diff --git a/src/mainboard/google/brox/variants/lotso/overridetree.cb b/src/mainboard/google/brox/variants/lotso/overridetree.cb
index e81848d..ae438f5 100644
--- a/src/mainboard/google/brox/variants/lotso/overridetree.cb
+++ b/src/mainboard/google/brox/variants/lotso/overridetree.cb
@@ -358,6 +358,7 @@
    			.clk_src = 3,
    			.clk_req = 3,
    			.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
+				.pcie_rp_aspm = ASPM_L1,
    		}"
    		chip soc/intel/common/block/pcie/rtd3
    			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"