Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43128 )
Change subject: haswell: Automatically check if Intel GbE is to be enabled ......................................................................
haswell: Automatically check if Intel GbE is to be enabled
If the Intel in-PCH GbE MAC is enabled in the devicetree, then tell MRC to enable it as well. No one can ever forget to set this option anymore!
Change-Id: I946af36d16c94bb1a0f146604d0329fe6d6ce7e2 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asrock/b85m_pro4/romstage.c M src/mainboard/lenovo/t440p/romstage.c M src/northbridge/intel/haswell/romstage.c 3 files changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/43128/1
diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index 6a71abb..9bdb8dd 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -28,7 +28,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { pei_data->ec_present = 0; - pei_data->gbe_enable = 1;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index c4baf7f..a1a66d3 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -49,7 +49,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { pei_data->ec_present = 1; - pei_data->gbe_enable = 1;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 014306d..40a4e38 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -3,6 +3,7 @@ #include <arch/romstage.h> #include <console/console.h> #include <cf9_reset.h> +#include <device/device.h> #include <timestamp.h> #include <cpu/x86/lapic.h> #include <cbmem.h> @@ -37,6 +38,8 @@ /* The romstage entry point for this platform is not mainboard-specific, hence the name */ void mainboard_romstage_entry(void) { + const struct device *gbe = pcidev_on_root(0x19, 0); + int wake_from_s3;
struct pei_data pei_data = { @@ -53,6 +56,7 @@ .temp_mmio_base = 0xfed08000, .system_type = get_pch_platform_type(), .tseg_size = CONFIG_SMM_TSEG_SIZE, + .gbe_enable = gbe && gbe->enabled, .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH), .max_ddr3_freq = 1600, };
Hello Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43128
to look at the new patch set (#2).
Change subject: haswell: Automatically check if Intel GbE is to be enabled ......................................................................
haswell: Automatically check if Intel GbE is to be enabled
If the Intel in-PCH GbE MAC is enabled in the devicetree, then tell MRC to enable it as well. No one can ever forget to set this option anymore!
Change-Id: I946af36d16c94bb1a0f146604d0329fe6d6ce7e2 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asrock/b85m_pro4/romstage.c M src/mainboard/lenovo/t440p/romstage.c M src/northbridge/intel/haswell/romstage.c 3 files changed, 4 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/43128/2
Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43128 )
Change subject: haswell: Automatically check if Intel GbE is to be enabled ......................................................................
Patch Set 2: Code-Review+1
Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43128 )
Change subject: haswell: Automatically check if Intel GbE is to be enabled ......................................................................
Patch Set 3: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43128 )
Change subject: haswell: Automatically check if Intel GbE is to be enabled ......................................................................
haswell: Automatically check if Intel GbE is to be enabled
If the Intel in-PCH GbE MAC is enabled in the devicetree, then tell MRC to enable it as well. No one can ever forget to set this option anymore!
Change-Id: I946af36d16c94bb1a0f146604d0329fe6d6ce7e2 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43128 Reviewed-by: Nico Huber nico.h@gmx.de Reviewed-by: Tristan Corrick tristan@corrick.kiwi Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/asrock/b85m_pro4/romstage.c M src/mainboard/lenovo/t440p/romstage.c M src/northbridge/intel/haswell/romstage.c 3 files changed, 4 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Tristan Corrick: Looks good to me, but someone else must approve
diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index 6a71abb..9bdb8dd 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -28,7 +28,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { pei_data->ec_present = 0; - pei_data->gbe_enable = 1;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index e83530a..8c2c5b6 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -49,7 +49,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) { pei_data->ec_present = 1; - pei_data->gbe_enable = 1;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = { /* Length, Enable, OCn#, Location */ diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 2961299..7016fd9 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -3,6 +3,7 @@ #include <arch/romstage.h> #include <console/console.h> #include <cf9_reset.h> +#include <device/device.h> #include <timestamp.h> #include <cpu/x86/lapic.h> #include <cbmem.h> @@ -37,6 +38,8 @@ /* The romstage entry point for this platform is not mainboard-specific, hence the name */ void mainboard_romstage_entry(void) { + const struct device *gbe = pcidev_on_root(0x19, 0); + int wake_from_s3;
struct pei_data pei_data = { @@ -53,6 +56,7 @@ .temp_mmio_base = 0xfed08000, .system_type = get_pch_platform_type(), .tseg_size = CONFIG_SMM_TSEG_SIZE, + .gbe_enable = gbe && gbe->enabled, .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH), .max_ddr3_freq = 1600, };
-
Angel Pons (Code Review) -
Nico Huber (Code Review)
-
Tristan Corrick (Code Review)