Attention is currently required from: Felix Singer, Raul Rangel, Furquan Shaikh, Paul Menzel, Angel Pons, Subrata Banik, Kyösti Mälkki, Patrick Rudolph, Jason Glenesk, Matt Delco, Nico Huber, Marshall Dawson, Tim Wawrzynczak, Felix Held. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57886 )
Change subject: acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table ......................................................................
Patch Set 8:
(15 comments)
File src/cpu/intel/common/common_init.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062): https://review.coreboot.org/c/coreboot/+/57886/comment/c63929c7_6ed600bd PS8, Line 108: config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 0, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062): https://review.coreboot.org/c/coreboot/+/57886/comment/1a2ab5d9_0e59a0ae PS8, Line 110: config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 16, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062): https://review.coreboot.org/c/coreboot/+/57886/comment/180a50f3_90fb1d39 PS8, Line 111: config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 24, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062): https://review.coreboot.org/c/coreboot/+/57886/comment/323f162d_bf3daec3 PS8, Line 112: config->entries[CPPC_GUARANTEED_PERF] = CPPC_REG_MSR(IA32_HWP_CAPABILITIES, 8, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062): https://review.coreboot.org/c/coreboot/+/57886/comment/1abb7cc3_f91bf6d9 PS8, Line 128: config->entries[CPPC_AUTO_ACTIVITY_WINDOW] = CPPC_REG_MSR(IA32_HWP_REQUEST, 32, 10); line over 96 characters
File src/soc/amd/cezanne/cppc.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062): https://review.coreboot.org/c/coreboot/+/57886/comment/21272585_68b7081b PS8, Line 18: config->entries[CPPC_HIGHEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062): https://review.coreboot.org/c/coreboot/+/57886/comment/90153ddb_4cb4a794 PS8, Line 19: config->entries[CPPC_NOMINAL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062): https://review.coreboot.org/c/coreboot/+/57886/comment/02d178fc_21968fd4 PS8, Line 20: config->entries[CPPC_LOWEST_NONL_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOW_NON_LIN_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062): https://review.coreboot.org/c/coreboot/+/57886/comment/9b6af4cb_cc93428d PS8, Line 21: config->entries[CPPC_LOWEST_PERF] = CPPC_REG_MSR(MSR_CPPC_CAPABILITY_1, SHIFT_CPPC_CAPABILITY_1_LOWEST_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062): https://review.coreboot.org/c/coreboot/+/57886/comment/bcda7aeb_e485e46b PS8, Line 23: config->entries[CPPC_DESIRED_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_DES_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062): https://review.coreboot.org/c/coreboot/+/57886/comment/2b1dd3ad_095424e4 PS8, Line 24: config->entries[CPPC_MIN_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MIN_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062): https://review.coreboot.org/c/coreboot/+/57886/comment/7c875dce_0e44a241 PS8, Line 25: config->entries[CPPC_MAX_PERF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_MAX_PERF, 8); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062): https://review.coreboot.org/c/coreboot/+/57886/comment/dbd34080_01168e28 PS8, Line 29: config->entries[CPPC_REF_PERF_COUNTER] = CPPC_REG_MSR(MSR_MAX_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062): https://review.coreboot.org/c/coreboot/+/57886/comment/9a1bc360_9df7cba0 PS8, Line 30: config->entries[CPPC_DELIVERED_PERF_COUNTER] = CPPC_REG_MSR(MSR_ACTUAL_PERFORMANCE_FREQUENCY_CLOCK_COUNT, 0, 64); line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-130062): https://review.coreboot.org/c/coreboot/+/57886/comment/72d7bff0_dd86b114 PS8, Line 39: config->entries[CPPC_PERF_PREF] = CPPC_REG_MSR(MSR_CPPC_REQUEST, SHIFT_CPPC_REQUEST_ENERGY_PERF_PREF, 8); line over 96 characters