Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30095
Change subject: mb/google/sarien: Use meaningful Satamode ......................................................................
mb/google/sarien: Use meaningful Satamode
Define Satamode to AHCI mode instead of 0, make devicetree more readable.
BUG=N/A
Change-Id: I903545d9487c1409f9008407fe5bee6aa4959b98 Signed-off-by: Lijian Zhao lijian.zhao@intel.com --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb 2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/30095/1
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index f487979..26d2153 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -17,7 +17,7 @@ register "SaGv" = "3" register "HeciEnabled" = "1" register "SataSalpSupport" = "1" - register "SataMode" = "0" + register "SataMode" = "Sata_AHCI" register "SataPortsEnable[0]" = "0" register "SataPortsEnable[1]" = "1" register "SataPortsEnable[2]" = "1" diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 5004abf..c5733fb 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -17,7 +17,7 @@ register "SaGv" = "3" register "HeciEnabled" = "1" register "SataSalpSupport" = "1" - register "SataMode" = "0" + register "SataMode" = "Sata_AHCI" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsEnable[2]" = "1"