[M] Change in coreboot[main]: soc/intel/common/block/pmc: Add GPE1 functions

[Cliff Huang (Code Review)]

Attention is currently required from: Anil Kumar K, Bora Guvendik, Felix Held, Hannah Williams, Jamie Ryu, Subrata Banik.

Cliff Huang has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84104?usp=email )

Change subject: soc/intel/common/block/pmc: Add GPE1 functions
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Patch Set 11:

(1 comment)

File src/soc/intel/common/block/include/intelblocks/pmclib.h:

https://review.coreboot.org/c/coreboot/+/84104/comment/f52311e5_71a3288f?usp... :
PS11, Line 241: gpe0_mask
> > Subrata,  […]

Subrata,

Thx! All GPE STS bits are cleared during SMM initialization and SMI GPE handler.  In addition, all GPE EN bits are cleared during post MP init. Both GPE1 STS and EN bits are cleared when the kconfig is enabled in this code review as you mentioned. Sorry that I might not be specific for my question, the need of introducing mask array is to extend 'pmc_disable_std_gpe(PME_B0_EN);' to also disable the corresponding GPE1 EN bits. Even if we extend current 32-bit mask to array here to cover all GPE0/GPE1 bits, unlike Intel common PME_BE0_EN that defined in src/soc/intel/common/pch/include/intelpch/gpe.h, GPE1 bit defines are SOC specific and shouldn't be used here. Meanwhile, I also want to explore other approaches.