Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63471 )
Change subject: soc/intel/common: use gpmr api in common drivers ......................................................................
soc/intel/common: use gpmr api in common drivers
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: I00ac667e8d3f2ccefd8d51a8150a989fc8e5c7e2 --- M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/lpc/Kconfig M src/soc/intel/common/block/lpc/lpc_lib.c M src/soc/intel/common/block/smbus/tco.c M src/soc/intel/common/pch/Kconfig M src/soc/intel/common/pch/lockdown/lockdown.c 6 files changed, 23 insertions(+), 42 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/63471/1
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 5a76df3..8bd9485 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -11,8 +11,8 @@ #include <commonlib/helpers.h> #include <cpu/x86/mtrr.h> #include <fast_spi_def.h> -#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/gpmr.h> #include <lib.h> #include <soc/pci_devs.h> #include <spi_flash.h> @@ -325,7 +325,7 @@ #endif
/* Configure Source decode for Extended BIOS Region */ - if (dmi_enable_gpmr(CONFIG_EXT_BIOS_WIN_BASE, CONFIG_EXT_BIOS_WIN_SIZE, + if (enable_gpmr(CONFIG_EXT_BIOS_WIN_BASE, CONFIG_EXT_BIOS_WIN_SIZE, soc_get_spi_psf_destination_id()) == CB_ERR) return;
diff --git a/src/soc/intel/common/block/lpc/Kconfig b/src/soc/intel/common/block/lpc/Kconfig index d76620a..2fac5ff 100644 --- a/src/soc/intel/common/block/lpc/Kconfig +++ b/src/soc/intel/common/block/lpc/Kconfig @@ -12,9 +12,9 @@ By default COMA range to LPC is enable. COMB range to LPC is optional and should select based on platform dedicated selection.
-config SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI +config SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR bool - depends on SOC_INTEL_COMMON_BLOCK_DMI + depends on SOC_INTEL_COMMON_BLOCK_GPMR help - Mirror LPC registers for IO/MMIO to their corresponding DMI registers. + Mirror LPC registers for IO/MMIO to their corresponding GPMR registers. Required for platforms starting from SPT. diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index 1393714..d57f1bc 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -7,6 +7,7 @@ #include <console/console.h> #include <device/pci.h> #include <device/pci_ops.h> +#include <intelblocks/gpmr.h> #include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> @@ -24,8 +25,8 @@ reg_io_enables = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES); io_enables |= reg_io_enables; pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, io_enables); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) - pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR)) + gpmr_write32(GPMR_LPCIOE, io_enables);
return io_enables; } @@ -42,8 +43,8 @@ reg_io_ranges = lpc_get_fixed_io_decode() & ~mask; io_ranges |= reg_io_ranges & mask; pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, io_ranges); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) - pcr_write16(PID_DMI, PCR_DMI_LPCIOD, io_ranges); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR)) + gpmr_write32(GPMR_LPCIOD, io_ranges);
return io_ranges; } @@ -112,8 +113,8 @@ lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num);
pci_write_config32(PCH_DEV_LPC, lgir_reg_offset, lgir); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1 + lgir_reg_num * 4, lgir); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR)) + gpmr_write32(GPMR_LPCLGIR1 + lgir_reg_num * 4, lgir);
printk(BIOS_DEBUG, "LPC: Opened IO window LGIR%d: base %llx size %x\n", @@ -147,8 +148,8 @@ lgmr = (base & LPC_LGMR_ADDR_MASK) | LPC_LGMR_EN;
pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_MEM_RANGE, lgmr); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) - pcr_write32(PID_DMI, PCR_DMI_LPCGMR, lgmr); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR)) + gpmr_write32(GPMR_LPCGMR, lgmr); }
/* @@ -248,8 +249,8 @@ /* Set in PCI generic decode range registers */ for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) { pci_write_config32(PCH_DEV_LPC, LPC_GENERIC_IO_RANGE(i), gen_io_dec[i]); - if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI)) - pcr_write32(PID_DMI, PCR_DMI_LPCLGIR1 + i * 4, gen_io_dec[i]); + if (CONFIG(SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR)) + gpmr_write32(GPMR_LPCLGIR1 + i * 4, gen_io_dec[i]); } }
diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 518541b..1ca8842 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -7,6 +7,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> +#include <intelblocks/gpmr.h> #include <intelblocks/pcr.h> #include <intelblocks/pmclib.h> #include <intelblocks/tco.h> @@ -16,10 +17,6 @@ #include <soc/pm.h> #include <soc/smbus.h>
-#define PCR_DMI_TCOBASE 0x2778 -/* Enable TCO I/O range decode. */ -#define TCOEN (1 << 1) - /* SMBUS TCO base address. */ #define TCOBASE 0x50 #define TCOCTL 0x54 @@ -122,10 +119,8 @@ /* Enable TCO in SMBUS */ pci_write_config32(dev, TCOCTL, reg32 | TCO_BASE_EN);
- /* - * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] - */ - pcr_write32(PID_DMI, PCR_DMI_TCOBASE, tcobase | TCOEN); + /* Program TCO Base Address */ + gpmr_write32(GPMR_TCOBASE, tcobase | GPMR_TCOEN); }
/* diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index 6ccf79d..7951298 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -33,7 +33,7 @@ select SOC_INTEL_COMMON_BLOCK_GPMR select SOC_INTEL_COMMON_BLOCK_ITSS select SOC_INTEL_COMMON_BLOCK_LPC - select SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_DMI + select SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR select SOC_INTEL_COMMON_BLOCK_P2SB select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_PMC diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index 5ab0611..7f7b8eb 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -2,10 +2,10 @@
#include <bootstate.h> #include <intelblocks/cfg.h> -#include <intelblocks/dmi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/pcr.h> #include <intelpch/lockdown.h> +#include <intelblocks/gpmr.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <soc/soc_chip.h> @@ -27,23 +27,8 @@
static void dmi_lockdown_cfg(void) { - /* - * GCS reg of DMI - * - * When set, prevents GCS.BBS from being changed - * GCS.BBS: (Boot BIOS Strap) This field determines the destination - * of accesses to the BIOS memory range. - * Bits Description - * "0b": SPI - * "1b": LPC/eSPI - */ - pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); - - /* - * Set Secure Register Lock (SRL) bit in DMI control register to lock - * DMI configuration. - */ - pcr_or32(PID_DMI, PCR_DMI_DMICTL, PCR_DMI_DMICTL_SRLOCK); + gpmr_or32(GPMR_GCS, GPMR_GCS_BILD); + gpmr_or32(GPMR_DMICTL, GPMR_DMICTL_SRLOCK); }
static void fast_spi_lockdown_cfg(int chipset_lockdown)
-
Wonkyu Kim (Code Review)