Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31603
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
mainboard: Add ASRock H110M-DVS
This board is compatible with Intel Skylake and Kabylake generation processors. This patch contains the minimum configuration for booting and stable operation of the OS. It is based on Intel RVP8 mainboard.
Intel FSP2.0 is used to initialize CPU and PCH. Graphics init with libgfxinit.
Work: - Integrated graphics (only DVI port); - PEG x16 (FSP must be configured with BCT to enable PEG); - all PCIe x1 slots; - all USB and SATA ports; - SuperIO COM port for console. TODO: - onboard audio; - other SuperIO functions; - onboard network chip; - documentation.
Tested on Intel Core i5-6600 processor with Seabios and Tianocore as a payload; booting Ubuntu 16.04.2 with Linux kernel 4.15
Change-Id: I69396edc50948cf1d0da649241ce92171d32daf7 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/mainboard/asrock/h110m/Kconfig A src/mainboard/asrock/h110m/Kconfig.name A src/mainboard/asrock/h110m/Makefile.inc A src/mainboard/asrock/h110m/acpi/dptf.asl A src/mainboard/asrock/h110m/acpi/ec.asl A src/mainboard/asrock/h110m/acpi/mainboard.asl A src/mainboard/asrock/h110m/acpi/superio.asl A src/mainboard/asrock/h110m/acpi_tables.c A src/mainboard/asrock/h110m/board_info.txt A src/mainboard/asrock/h110m/bootblock.c A src/mainboard/asrock/h110m/cmos.default A src/mainboard/asrock/h110m/cmos.layout A src/mainboard/asrock/h110m/dsdt.asl A src/mainboard/asrock/h110m/gma-mainboard.ads A src/mainboard/asrock/h110m/hda_verb.c A src/mainboard/asrock/h110m/mainboard.c A src/mainboard/asrock/h110m/ramstage.c A src/mainboard/asrock/h110m/romstage.c A src/mainboard/asrock/h110m/spd/Makefile.inc A src/mainboard/asrock/h110m/spd/spd.h A src/mainboard/asrock/h110m/spd/spd_util.c A src/mainboard/asrock/h110m/variants/baseboard/devicetree.cb A src/mainboard/asrock/h110m/variants/dvs/data.vbt A src/mainboard/asrock/h110m/variants/dvs/include/variant/gpio.h A src/mainboard/asrock/h110m/variants/dvs/include/variant/hda_verb.h A src/mainboard/asrock/h110m/variants/dvs/overridetree.cb 26 files changed, 1,477 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31603/1
diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig new file mode 100644 index 0000000..3629d7c --- /dev/null +++ b/src/mainboard/asrock/h110m/Kconfig @@ -0,0 +1,93 @@ +if BOARD_ASROCK_H110M_DVS + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SYSTEM_TYPE_DESKTOP + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select SKYLAKE_SOC_PCH_H + select MAINBOARD_USES_FSP2_0 + select GENERIC_SPD_BIN + select TSC_MONOTONIC_TIMER + select SERIRQ_CONTINUOUS_MODE + select SUPERIO_NUVOTON_NCT6791D + select SUPERIO_NUVOTON_NCT6776_COM_A + select HAVE_SMI_HANDLER + select REALTEK_8168_RESET + select RT8168_SET_LED_MODE + +choice + prompt "Processor family" + default USE_SOC_INTEL_SKYLAKE + +config USE_SOC_INTEL_SKYLAKE + bool "Skylake" + select SOC_INTEL_SKYLAKE + +config USE_SOC_INTEL_KABYLAKE + bool "Kabylake" + select SOC_INTEL_KABYLAKE + +endchoice + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "asrock/h110m" + +config VARIANT_DIR + string + default "dvs" if BOARD_ASROCK_H110M_DVS + +config MAINBOARD_PART_NUMBER + string + default "H110M" + +config MAINBOARD_FAMILY + string + default "ASROCK" + +config MAX_CPUS + int + default 8 + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config IFD_BIN_PATH + string + depends on HAVE_IFD_BIN + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.dvs.bin" if BOARD_ASROCK_H110M_DVS + +config ME_BIN_PATH + string + depends on HAVE_ME_BIN + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/me.dvs.bin" if BOARD_ASROCK_H110M_DVS + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0xd00 + +config DIMM_SPD_SIZE + int + default 512 #DDR4 + +# This is overridden if CMOS is used for configuration values. +config MAINBOARD_POWER_ON_AFTER_POWER_FAIL + bool + default n + +endif diff --git a/src/mainboard/asrock/h110m/Kconfig.name b/src/mainboard/asrock/h110m/Kconfig.name new file mode 100644 index 0000000..34c1a3c --- /dev/null +++ b/src/mainboard/asrock/h110m/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASROCK_H110M_DVS + bool "H110M-DVS" diff --git a/src/mainboard/asrock/h110m/Makefile.inc b/src/mainboard/asrock/h110m/Makefile.inc new file mode 100644 index 0000000..558af91 --- /dev/null +++ b/src/mainboard/asrock/h110m/Makefile.inc @@ -0,0 +1,29 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd +bootblock-y += bootblock.c + +ramstage-y += mainboard.c +ramstage-y += ramstage.c +ramstage-y += hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads + +subdirs-y += variants/baseboard +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/asrock/h110m/acpi/dptf.asl b/src/mainboard/asrock/h110m/acpi/dptf.asl new file mode 100644 index 0000000..4453f3b --- /dev/null +++ b/src/mainboard/asrock/h110m/acpi/dptf.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 98 +#define DPTF_CPU_CRITICAL 125 +#define DPTF_CPU_ACTIVE_AC0 91 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 83 +#define DPTF_CPU_ACTIVE_AC3 80 +#define DPTF_CPU_ACTIVE_AC4 75 + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { _SB.PCI0.B0D4, _SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 10000, /* PowerLimitMinimum */ + 31000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 65000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/skylake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/asrock/h110m/acpi/ec.asl b/src/mainboard/asrock/h110m/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asrock/h110m/acpi/ec.asl diff --git a/src/mainboard/asrock/h110m/acpi/mainboard.asl b/src/mainboard/asrock/h110m/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asrock/h110m/acpi/mainboard.asl diff --git a/src/mainboard/asrock/h110m/acpi/superio.asl b/src/mainboard/asrock/h110m/acpi/superio.asl new file mode 100644 index 0000000..b671e3c --- /dev/null +++ b/src/mainboard/asrock/h110m/acpi/superio.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick tristan@corrick.kiwi + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define NCT6776_SHOW_PP +#define NCT6776_SHOW_SP1 +#define NCT6776_SHOW_KBC +#define NCT6776_SHOW_HWM + +#undef NCT6776_SHOW_GPIO + +#include <superio/nuvoton/nct6776/acpi/superio.asl> diff --git a/src/mainboard/asrock/h110m/acpi_tables.c b/src/mainboard/asrock/h110m/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asrock/h110m/acpi_tables.c diff --git a/src/mainboard/asrock/h110m/board_info.txt b/src/mainboard/asrock/h110m/board_info.txt new file mode 100644 index 0000000..7b7f3d4 --- /dev/null +++ b/src/mainboard/asrock/h110m/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/H110M-DVS%20R2.0/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: n +Release year: 2015 diff --git a/src/mainboard/asrock/h110m/bootblock.c b/src/mainboard/asrock/h110m/bootblock.c new file mode 100644 index 0000000..771ce13 --- /dev/null +++ b/src/mainboard/asrock/h110m/bootblock.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/gpio.h> +#include <variant/gpio.h> +#include <console/console.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6791d/nct6791d.h> + +static void early_config_superio(void) +{ + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT6791D_SP1); + nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} + +void bootblock_mainboard_early_init(void) +{ + early_config_superio(); + printk(BIOS_INFO, "Early init console SIO!\n"); +} diff --git a/src/mainboard/asrock/h110m/cmos.default b/src/mainboard/asrock/h110m/cmos.default new file mode 100644 index 0000000..cd8bd47 --- /dev/null +++ b/src/mainboard/asrock/h110m/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Spew +power_on_after_fail=Disable +nmi=Enable diff --git a/src/mainboard/asrock/h110m/cmos.layout b/src/mainboard/asrock/h110m/cmos.layout new file mode 100644 index 0000000..916db62 --- /dev/null +++ b/src/mainboard/asrock/h110m/cmos.layout @@ -0,0 +1,125 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/asrock/h110m/dsdt.asl b/src/mainboard/asrock/h110m/dsdt.asl new file mode 100644 index 0000000..ca8c327 --- /dev/null +++ b/src/mainboard/asrock/h110m/dsdt.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (_SB) { + Device (PCI0) + { + /* Image processing unit */ + #include <soc/intel/skylake/acpi/ipu.asl> + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + // Dynamic Platform Thermal Framework + #include "acpi/dptf.asl" + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/asrock/h110m/gma-mainboard.ads b/src/mainboard/asrock/h110m/gma-mainboard.ads new file mode 100644 index 0000000..b217608 --- /dev/null +++ b/src/mainboard/asrock/h110m/gma-mainboard.ads @@ -0,0 +1,32 @@ +-- +-- This file is part of the coreboot project. +-- +-- Copyright (C) 2018 Tristan Corrick tristan@corrick.kiwi +-- Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, + HDMI3, + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/h110m/hda_verb.c b/src/mainboard/asrock/h110m/hda_verb.c new file mode 100644 index 0000000..b219987 --- /dev/null +++ b/src/mainboard/asrock/h110m/hda_verb.c @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * (Written by Naresh G Solanki naresh.solanki@intel.com for Intel Corp.) + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "variant/hda_verb.h" diff --git a/src/mainboard/asrock/h110m/mainboard.c b/src/mainboard/asrock/h110m/mainboard.c new file mode 100644 index 0000000..4c1c6cd --- /dev/null +++ b/src/mainboard/asrock/h110m/mainboard.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick tristan@corrick.kiwi + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asrock/h110m/ramstage.c b/src/mainboard/asrock/h110m/ramstage.c new file mode 100644 index 0000000..155d347 --- /dev/null +++ b/src/mainboard/asrock/h110m/ramstage.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <soc/ramstage.h> +#include <variant/gpio.h> + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + params->CdClock = 3; + /* Enable Virtual Channel 1 */ + params->PchHdaVcType = 0x1; +} diff --git a/src/mainboard/asrock/h110m/romstage.c b/src/mainboard/asrock/h110m/romstage.c new file mode 100644 index 0000000..64c5468 --- /dev/null +++ b/src/mainboard/asrock/h110m/romstage.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/api.h> +#include <gpio.h> +#include "gpio.h" +#include <soc/romstage.h> +#include <soc/gpio.h> +#include "spd/spd.h" +#include <string.h> +#include <spd_bin.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = { 0x50, 0x51, 0x52, 0x53, }, + }; + + mem_cfg = &mupd->FspmConfig; + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; + mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; + mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + dump_spd_info(&blk); + + /* use virtual channel 1 for the dmi interface of the PCH */ + mupd->FspmTestConfig.DmiVc1 = 1; + + /* desktop type */ + mem_cfg->UserBd = BOARD_TYPE_DESKTOP; +} diff --git a/src/mainboard/asrock/h110m/spd/Makefile.inc b/src/mainboard/asrock/h110m/spd/Makefile.inc new file mode 100644 index 0000000..cdf469e --- /dev/null +++ b/src/mainboard/asrock/h110m/spd/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## Copyright (C) 2015 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd_util.c \ No newline at end of file diff --git a/src/mainboard/asrock/h110m/spd/spd.h b/src/mainboard/asrock/h110m/spd/spd.h new file mode 100644 index 0000000..c24baa0 --- /dev/null +++ b/src/mainboard/asrock/h110m/spd/spd.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#include <gpio.h> +#include <variant/gpio.h> + +#define RCOMP_TARGET_PARAMS 0x5 + +void mainboard_fill_dq_map_data(void *dq_map_ptr); +void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); +#endif diff --git a/src/mainboard/asrock/h110m/spd/spd_util.c b/src/mainboard/asrock/h110m/spd/spd_util.c new file mode 100644 index 0000000..64c92cc --- /dev/null +++ b/src/mainboard/asrock/h110m/spd/spd_util.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <arch/byteorder.h> +#include <console/console.h> +#include <stdint.h> +#include <string.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include "spd.h" + +void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 200, 81, 162 }; + memcpy(rcomp_ptr, RcompResistor, + sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { + 100, 40, 40, 23, 40 }; + + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} diff --git a/src/mainboard/asrock/h110m/variants/baseboard/devicetree.cb b/src/mainboard/asrock/h110m/variants/baseboard/devicetree.cb new file mode 100644 index 0000000..edff72c --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/baseboard/devicetree.cb @@ -0,0 +1,251 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Intel Corporation. +## Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable DPTF + register "dptf_enable" = "1" + + # FSP Configuration + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "HeciEnabled" = "0" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "SaGv" = "SaGv_Enabled" + register "PmTimerDisabled" = "0" + register "SerialIrqConfigSirqMode" = "0x01" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled + register "SerialIrqConfigSirqEnable" = "0x01" + + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x10, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0 ,\ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + + register "EnableLan" = "0" + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + + # Must leave UART0 enabled or SD/eMMC will not work as PCI + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0a" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + + register "PmTimerDisabled" = "0" + + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoSkipInit, \ + [PchSerialIoIndexI2C1] = PchSerialIoSkipInit, \ + [PchSerialIoIndexI2C2] = PchSerialIoSkipInit, \ + [PchSerialIoIndexI2C3] = PchSerialIoSkipInit, \ + [PchSerialIoIndexI2C4] = PchSerialIoSkipInit, \ + [PchSerialIoIndexI2C5] = PchSerialIoSkipInit, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoSkipInit, \ + [PchSerialIoIndexUart0] = PchSerialIoSkipInit, \ + [PchSerialIoIndexUart1] = PchSerialIoSkipInit, \ + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ + }" + + # PL2 override 91W + register "tdp_pl2_override" = "91" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on # Host Bridge + subsystemid 0x1849 0x191f + end + device pci 01.0 on # PEG + subsystemid 0x1849 0x191f + end + device pci 02.0 on # Integrated Graphics Device + subsystemid 0x1849 0x1912 + end + device pci 14.0 on # USB xHCI + subsystemid 0x1849 0xa131 + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on # Thermal Subsystem + subsystemid 0x1849 0xa131 + end + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1849 0xa131 + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on # SATA + subsystemid 0x1849 0xa102 + end + device pci 19.0 off end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 off end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 off end # Power Management Controller + device pci 1f.3 off end # Intel HDA + device pci 1f.4 off end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/asrock/h110m/variants/dvs/data.vbt b/src/mainboard/asrock/h110m/variants/dvs/data.vbt new file mode 100644 index 0000000..fb03cca --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/dvs/data.vbt Binary files differ diff --git a/src/mainboard/asrock/h110m/variants/dvs/include/variant/gpio.h b/src/mainboard/asrock/h110m/variants/dvs/include/variant/gpio.h new file mode 100644 index 0000000..77a11bd --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/dvs/include/variant/gpio.h @@ -0,0 +1,262 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIO_D3H_H +#define _GPIO_D3H_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#define H110_PAD_DW0_DW1_CFG(val, config0, config1) \ + _PAD_CFG_STRUCT(val, config0, config1) + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ + H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ + H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ + H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ + H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ + H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ + H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ + H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ + H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ + H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ + H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ + H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ + H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ + H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ + /* GPIO Group GPP_B */ + H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B4, 0x84000502, 0x00000034), /* CPU_GP3 */ + H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B12, 0x44000600, 0x0000003c), /* SLP_S0# */ + H110_PAD_DW0_DW1_CFG(GPP_B13, 0x44000600, 0x0000003d), /* PLTRST# */ + H110_PAD_DW0_DW1_CFG(GPP_B14, 0x84000600, 0x0000103e), /* SPKR */ + H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B23, 0x84000a01, 0x00001047), /* PCHHOT# */ + /* GPIO Group GPP_C */ + H110_PAD_DW0_DW1_CFG(GPP_C0, 0x44000502, 0x00000048), /* SMBCLK */ + H110_PAD_DW0_DW1_CFG(GPP_C1, 0x44000502, 0x00000049), /* SMBDATA */ + H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C3, 0x44000502, 0x0000004b), /* SML0CLK */ + H110_PAD_DW0_DW1_CFG(GPP_C4, 0x44000502, 0x0000004c), /* SML0DATA */ + H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + H110_PAD_DW0_DW1_CFG(GPP_C8, 0x84000502, 0x00000050), /* UART0_RXD */ + H110_PAD_DW0_DW1_CFG(GPP_C9, 0x84000600, 0x00000051), /* UART0_TXD */ + H110_PAD_DW0_DW1_CFG(GPP_C10, 0x84000600, 0x00000052), /* UART0_RTS# */ + H110_PAD_DW0_DW1_CFG(GPP_C11, 0x84000502, 0x00000053), /* UART0_CTS# */ + H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C20, 0x84000502, 0x0000005c), /* UART2_RXD */ + H110_PAD_DW0_DW1_CFG(GPP_C21, 0x84000600, 0x0000005d), /* UART2_TXD */ + H110_PAD_DW0_DW1_CFG(GPP_C22, 0x84000600, 0x0000005e), /* UART2_RTS# */ + H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ + /* GPIO Group GPP_D */ + H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D5, 0x84000402, 0x00000065), /* I2S_SFRM */ + H110_PAD_DW0_DW1_CFG(GPP_D6, 0x84000600, 0x00000066), /* I2S_TXD */ + H110_PAD_DW0_DW1_CFG(GPP_D7, 0x84000502, 0x00000067), /* I2S_RXD */ + H110_PAD_DW0_DW1_CFG(GPP_D8, 0x84000402, 0x00000068), /* I2S_SCLK */ + H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D19, 0x84000500, 0x00003073), /* DMIC_CLK0 */ + H110_PAD_DW0_DW1_CFG(GPP_D20, 0x84000500, 0x00003074), /* DMIC_DATA0 */ + H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ + /* GPIO Group GPP_E */ + H110_PAD_DW0_DW1_CFG(GPP_E0, 0x84000502, 0x00003018), /* SATAXPCIE0 */ + H110_PAD_DW0_DW1_CFG(GPP_E1, 0x84000502, 0x00003019), /* SATAXPCIE1 */ + H110_PAD_DW0_DW1_CFG(GPP_E2, 0x84000502, 0x0000301a), /* SATAXPCIE2 */ + H110_PAD_DW0_DW1_CFG(GPP_E3, 0x84000500, 0x0000001b), /* CPU_GP0 */ + H110_PAD_DW0_DW1_CFG(GPP_E4, 0x84000500, 0x0000001c), /* SATA_DEVSLP0 */ + H110_PAD_DW0_DW1_CFG(GPP_E5, 0x84000500, 0x0000001d), /* SATA_DEVSLP1 */ + H110_PAD_DW0_DW1_CFG(GPP_E6, 0x84000500, 0x0000001e), /* SATA_DEVSLP2 */ + H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E8, 0x84000600, 0x00000020), /* SATA_LED# */ + H110_PAD_DW0_DW1_CFG(GPP_E9, 0x44000502, 0x00000021), /* USB_OC0# */ + H110_PAD_DW0_DW1_CFG(GPP_E10, 0x44000502, 0x00000022), /* USB_OC1# */ + H110_PAD_DW0_DW1_CFG(GPP_E11, 0x44000502, 0x00000023), /* USB_OC2# */ + H110_PAD_DW0_DW1_CFG(GPP_E12, 0x44000502, 0x00000024), /* USB_OC3# */ + /* GPIO Group GPP_F */ + H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F1, 0x84000502, 0x00003026), /* SATAXPCIE4 */ + H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F15, 0x44000502, 0x00000034), /* USB_OC4# */ + H110_PAD_DW0_DW1_CFG(GPP_F16, 0x44000502, 0x00000035), /* USB_OC5# */ + H110_PAD_DW0_DW1_CFG(GPP_F17, 0x44000502, 0x00000036), /* USB_OC6# */ + H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ + /* GPIO Group GPP_G */ + H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G19, 0x84000500, 0x00000050), /* SMI# */ + H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */ + /* GPIO Group GPP_H */ + H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */ + /* GPIO Group GPD */ + H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD2, 0x00000602, 0x00003c1a), /* LAN_WAKE# */ + H110_PAD_DW0_DW1_CFG(GPD3, 0x04000502, 0x0000301b), /* PWRBTN# */ + H110_PAD_DW0_DW1_CFG(GPD4, 0x04000600, 0x0000001c), /* SLP_S3# */ + H110_PAD_DW0_DW1_CFG(GPD5, 0x04000600, 0x0000001d), /* SLP_S4# */ + H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD8, 0x04000600, 0x00000020), /* SUSCLK */ + H110_PAD_DW0_DW1_CFG(GPD9, 0x04000600, 0x00000021), /* SLP_WLAN# */ + H110_PAD_DW0_DW1_CFG(GPD10, 0x04000600, 0x00000022), /* SLP_S5# */ + H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */ + /* GPIO Group GPP_I */ + H110_PAD_DW0_DW1_CFG(GPP_I0, 0x84000502, 0x0000006d), /* DDPB_HPD0 */ + H110_PAD_DW0_DW1_CFG(GPP_I1, 0x84000502, 0x0000006e), /* DDPC_HPD1 */ + H110_PAD_DW0_DW1_CFG(GPP_I2, 0x84000500, 0x0000006f), /* DDPD_HPD2 */ + H110_PAD_DW0_DW1_CFG(GPP_I3, 0x84000502, 0x00000070), /* DDPE_HPD3 */ + H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_I5, 0x84000500, 0x00000072), /* DDPB_CTRLCLK */ + H110_PAD_DW0_DW1_CFG(GPP_I6, 0x84000500, 0x00001073), /* DDPB_CTRLDATA */ + H110_PAD_DW0_DW1_CFG(GPP_I7, 0x84000500, 0x00000074), /* DDPC_CTRLCLK */ + H110_PAD_DW0_DW1_CFG(GPP_I8, 0x84000500, 0x00001075), /* DDPC_CTRLDATA */ + H110_PAD_DW0_DW1_CFG(GPP_I9, 0x84000500, 0x00000076), /* DDPD_CTRLCLK */ + H110_PAD_DW0_DW1_CFG(GPP_I10, 0x84000500, 0x00001077), /* DDPD_CTRLDATA */ +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + /* GPIO Group GPP_A */ + H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ + H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ + H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ + H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ + H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ + H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ + H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ + H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ + H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ + H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ + /* ---- */ + H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ + H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ + H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ +}; + +#endif diff --git a/src/mainboard/asrock/h110m/variants/dvs/include/variant/hda_verb.h b/src/mainboard/asrock/h110m/variants/dvs/include/variant/hda_verb.h new file mode 100644 index 0000000..746f0ef --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/dvs/include/variant/hda_verb.h @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * (Written by Naresh G Solanki naresh.solanki@intel.com for Intel Corp.) + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header ALC887 */ + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x10438445, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x0, 0x10438445), + AZALIA_PIN_CFG(0x0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x14, 0x01014020), + AZALIA_PIN_CFG(0x0, 0x15, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0x0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0x0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0x0, 0x1b, 0x02214030), + AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1d, 0x4026c629), + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0), + + /* coreboot specific header */ + 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */ + 0x80860101, + 0x00000004, + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + AZALIA_SUBVENDOR(0x2, 0x80860101), + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x05, 0x18560010), + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x06, 0x18560020), + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x07, 0x18560030) +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; +#endif diff --git a/src/mainboard/asrock/h110m/variants/dvs/overridetree.cb b/src/mainboard/asrock/h110m/variants/dvs/overridetree.cb new file mode 100644 index 0000000..9c3cd6d --- /dev/null +++ b/src/mainboard/asrock/h110m/variants/dvs/overridetree.cb @@ -0,0 +1,187 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/skylake + + # USB + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # SATA + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + + # PCH UART, SPI, I2C + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoSkipInit, \ + [PchSerialIoIndexI2C3] = PchSerialIoSkipInit, \ + [PchSerialIoIndexI2C4] = PchSerialIoSkipInit, \ + [PchSerialIoIndexI2C5] = PchSerialIoSkipInit, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoSkipInit, \ + [PchSerialIoIndexUart0] = PchSerialIoSkipInit, \ + [PchSerialIoIndexUart1] = PchSerialIoSkipInit, \ + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ + }" + + # Enable Root port 6(x1) for LAN. + register "PcieRpEnable[5]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[5]" = "1" + # Use SRCCLKREQ1# + register "PcieRpClkReqNumber[5]" = "1" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[5]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[5]" = "1" + # Use CLK SRC 1 + register "PcieRpClkSrcNumber[5]" = "1" + + # Enable Root port 5 (x1) for PCIE slot. + register "PcieRpEnable[4]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[4]" = "1" + # Use SRCCLKREQ2# + register "PcieRpClkReqNumber[4]" = "2" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[4]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[4]" = "1" + # Use CLK SRC 2 + register "PcieRpClkSrcNumber[4]" = "2" + # Use Hot Plug subsystem + register "PcieRpHotPlug[4]" = "1" + + # Enable Root port 7(x1) for PCIE slot. + register "PcieRpEnable[6]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[6]" = "1" + # Use SRCCLKREQ3# + register "PcieRpClkReqNumber[6]" = "3" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[6]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[6]" = "1" + # Use CLK SRC 3 + register "PcieRpClkSrcNumber[6]" = "3" + # Use Hot Plug subsystem + register "PcieRpHotPlug[6]" = "1" + + device domain 0 on + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 on end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x1a43 + chip superio/nuvoton/nct6791d + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel + # global + irq 0x1c = 0x10 + irq 0x27 = 0x10 + irq 0x2a = 0x64 + # parallel port + io 0x60 = 0x0378 + irq 0x70 = 7 + drq 0x74 = 4 # No DMA + irq 0xf0 = 0x3c # Printer mode + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # IR + io 0x60 = 0x02f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6..8 + device pnp 2e.8 off end # WDT1, WDT_MEM, GPIO 0, GPIO 1 + device pnp 2e.9 off end # GPIO 2, GPIO 3, GPIO 4, GPIO 5 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # Deep sleep + + end # superio/nuvoton/nct6791d + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM module + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31603 )
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
Patch Set 1:
(23 comments)
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/bootblock... File src/mainboard/asrock/h110m/bootblock.c:
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/bootblock... PS1, Line 26: const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT6791D_SP1); code indent should use tabs where possible
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/bootblock... PS1, Line 26: const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT6791D_SP1); please, no spaces at the start of a line
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/bootblock... PS1, Line 27: nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); code indent should use tabs where possible
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/bootblock... PS1, Line 27: nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); please, no spaces at the start of a line
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/variants/... File src/mainboard/asrock/h110m/variants/dvs/include/variant/gpio.h:
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/variants/... PS1, Line 23: _PAD_CFG_STRUCT(val, config0, config1) code indent should use tabs where possible
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/variants/... PS1, Line 23: _PAD_CFG_STRUCT(val, config0, config1) please, no spaces at the start of a line
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/variants/... PS1, Line 41: H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ line over 80 characters
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/variants/... PS1, Line 132: H110_PAD_DW0_DW1_CFG(GPP_E4, 0x84000500, 0x0000001c), /* SATA_DEVSLP0 */ line over 80 characters
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/variants/... PS1, Line 133: H110_PAD_DW0_DW1_CFG(GPP_E5, 0x84000500, 0x0000001d), /* SATA_DEVSLP1 */ line over 80 characters
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/variants/... PS1, Line 134: H110_PAD_DW0_DW1_CFG(GPP_E6, 0x84000500, 0x0000001e), /* SATA_DEVSLP2 */ line over 80 characters
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/variants/... PS1, Line 235: H110_PAD_DW0_DW1_CFG(GPP_I5, 0x84000500, 0x00000072), /* DDPB_CTRLCLK */ line over 80 characters
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/variants/... PS1, Line 236: H110_PAD_DW0_DW1_CFG(GPP_I6, 0x84000500, 0x00001073), /* DDPB_CTRLDATA */ line over 80 characters
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/variants/... PS1, Line 237: H110_PAD_DW0_DW1_CFG(GPP_I7, 0x84000500, 0x00000074), /* DDPC_CTRLCLK */ line over 80 characters
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/variants/... PS1, Line 238: H110_PAD_DW0_DW1_CFG(GPP_I8, 0x84000500, 0x00001075), /* DDPC_CTRLDATA */ line over 80 characters
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/variants/... PS1, Line 239: H110_PAD_DW0_DW1_CFG(GPP_I9, 0x84000500, 0x00000076), /* DDPD_CTRLCLK */ line over 80 characters
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/variants/... PS1, Line 240: H110_PAD_DW0_DW1_CFG(GPP_I10, 0x84000500, 0x00001077), /* DDPD_CTRLDATA */ line over 80 characters
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/variants/... PS1, Line 257: H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ line over 80 characters
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/variants/... PS1, Line 257: H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ code indent should use tabs where possible
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/variants/... PS1, Line 257: H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ please, no spaces at the start of a line
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/variants/... PS1, Line 258: H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ code indent should use tabs where possible
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/variants/... PS1, Line 258: H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ please, no spaces at the start of a line
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/variants/... PS1, Line 259: H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ code indent should use tabs where possible
https://review.coreboot.org/#/c/31603/1/src/mainboard/asrock/h110m/variants/... PS1, Line 259: H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ please, no spaces at the start of a line
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31603
to look at the new patch set (#2).
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
mainboard: Add ASRock H110M-DVS
This board is compatible with Intel Skylake and Kabylake generation processors. This patch contains the minimum configuration for booting and stable operation of the OS. It is based on Intel RVP8 mainboard.
Intel FSP2.0 is used to initialize CPU and PCH. Graphics init with libgfxinit.
Work: - Integrated graphics (only DVI port); - PEG x16 (FSP must be configured with BCT to enable PEG); - all PCIe x1 slots; - all USB and SATA ports; - SuperIO COM port for console. TODO: - onboard audio; - other SuperIO functions; - onboard network chip; - documentation.
Tested on Intel Core i5-6600 processor with Seabios and Tianocore as a payload; booting Ubuntu 16.04.2 with Linux kernel 4.15
Change-Id: I69396edc50948cf1d0da649241ce92171d32daf7 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/mainboard/asrock/h110m/Kconfig A src/mainboard/asrock/h110m/Kconfig.name A src/mainboard/asrock/h110m/Makefile.inc A src/mainboard/asrock/h110m/acpi/dptf.asl A src/mainboard/asrock/h110m/acpi/ec.asl A src/mainboard/asrock/h110m/acpi/mainboard.asl A src/mainboard/asrock/h110m/acpi/superio.asl A src/mainboard/asrock/h110m/acpi_tables.c A src/mainboard/asrock/h110m/board_info.txt A src/mainboard/asrock/h110m/bootblock.c A src/mainboard/asrock/h110m/cmos.default A src/mainboard/asrock/h110m/cmos.layout A src/mainboard/asrock/h110m/dsdt.asl A src/mainboard/asrock/h110m/gma-mainboard.ads A src/mainboard/asrock/h110m/hda_verb.c A src/mainboard/asrock/h110m/mainboard.c A src/mainboard/asrock/h110m/ramstage.c A src/mainboard/asrock/h110m/romstage.c A src/mainboard/asrock/h110m/spd/Makefile.inc A src/mainboard/asrock/h110m/spd/spd.h A src/mainboard/asrock/h110m/spd/spd_util.c A src/mainboard/asrock/h110m/variants/baseboard/devicetree.cb A src/mainboard/asrock/h110m/variants/dvs/data.vbt A src/mainboard/asrock/h110m/variants/dvs/include/variant/gpio.h A src/mainboard/asrock/h110m/variants/dvs/include/variant/hda_verb.h A src/mainboard/asrock/h110m/variants/dvs/overridetree.cb 26 files changed, 1,477 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31603/2
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31603 )
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
Patch Set 2:
(23 comments)
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/bootblock... File src/mainboard/asrock/h110m/bootblock.c:
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/bootblock... PS2, Line 26: const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT6791D_SP1); code indent should use tabs where possible
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/bootblock... PS2, Line 26: const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT6791D_SP1); please, no spaces at the start of a line
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/bootblock... PS2, Line 27: nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); code indent should use tabs where possible
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/bootblock... PS2, Line 27: nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); please, no spaces at the start of a line
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... File src/mainboard/asrock/h110m/variants/dvs/include/variant/gpio.h:
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 23: _PAD_CFG_STRUCT(val, config0, config1) code indent should use tabs where possible
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 23: _PAD_CFG_STRUCT(val, config0, config1) please, no spaces at the start of a line
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 41: H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ line over 80 characters
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 132: H110_PAD_DW0_DW1_CFG(GPP_E4, 0x84000500, 0x0000001c), /* SATA_DEVSLP0 */ line over 80 characters
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 133: H110_PAD_DW0_DW1_CFG(GPP_E5, 0x84000500, 0x0000001d), /* SATA_DEVSLP1 */ line over 80 characters
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 134: H110_PAD_DW0_DW1_CFG(GPP_E6, 0x84000500, 0x0000001e), /* SATA_DEVSLP2 */ line over 80 characters
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 235: H110_PAD_DW0_DW1_CFG(GPP_I5, 0x84000500, 0x00000072), /* DDPB_CTRLCLK */ line over 80 characters
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 236: H110_PAD_DW0_DW1_CFG(GPP_I6, 0x84000500, 0x00001073), /* DDPB_CTRLDATA */ line over 80 characters
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 237: H110_PAD_DW0_DW1_CFG(GPP_I7, 0x84000500, 0x00000074), /* DDPC_CTRLCLK */ line over 80 characters
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 238: H110_PAD_DW0_DW1_CFG(GPP_I8, 0x84000500, 0x00001075), /* DDPC_CTRLDATA */ line over 80 characters
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 239: H110_PAD_DW0_DW1_CFG(GPP_I9, 0x84000500, 0x00000076), /* DDPD_CTRLCLK */ line over 80 characters
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 240: H110_PAD_DW0_DW1_CFG(GPP_I10, 0x84000500, 0x00001077), /* DDPD_CTRLDATA */ line over 80 characters
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 257: H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ line over 80 characters
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 257: H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ code indent should use tabs where possible
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 257: H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN#/SUSPWRDNACK */ please, no spaces at the start of a line
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 258: H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ code indent should use tabs where possible
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 258: H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ please, no spaces at the start of a line
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 259: H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ code indent should use tabs where possible
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 259: H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ please, no spaces at the start of a line
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31603 )
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
Patch Set 2:
(10 comments)
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig File src/mainboard/asrock/h110m/Kconfig:
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig@1... PS2, Line 16: TSC_MONOTONIC_TIMER already selected in the skylake soc Kconfig
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig@2... PS2, Line 20: HAVE_SMI_HANDLER already selected in the skylake soc Kconfig
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig@2... PS2, Line 24: choice : prompt "Processor family" : default USE_SOC_INTEL_SKYLAKE : : config USE_SOC_INTEL_SKYLAKE : bool "Skylake" : select SOC_INTEL_SKYLAKE : : config USE_SOC_INTEL_KABYLAKE : bool "Kabylake" : select SOC_INTEL_KABYLAKE : : endchoice is making this distinction really needed? you end up using the kabylake FSP anyway iirc.
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig@4... PS2, Line 45: : config VARIANT_DIR : string : default "dvs" if BOARD_ASROCK_H110M_DVS remove until you add variants.
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig@7... PS2, Line 73: BOARD_ASROCK_H110M_DVS not needed.
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig@7... PS2, Line 78: BOARD_ASROCK_H110M_DVS not needed.
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig@8... PS2, Line 84: config DIMM_SPD_SIZE : int : default 512 #DDR4 not the scope of your patch but I don't think it ought to be defined here. Afaik the fsp has size expectation on the array passed and that is not board specific.
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... File src/mainboard/asrock/h110m/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 38: # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f : register "gen1_dec" = "0x00fc0801 I don't see a device decoding this range.
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 156: register "pirqa_routing" = "0x0b" : register "pirqb_routing" = "0x0a" : register "pirqc_routing" = "0x0b" : register "pirqd_routing" = "0x0b" : register "pirqe_routing" = "0x0b" : register "pirqf_routing" = "0x0b" : register "pirqg_routing" = "0x0b" : register "pirqh_routing" = "0x0b" already done at line 60.
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... File src/mainboard/asrock/h110m/variants/dvs/overridetree.cb:
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 1: ## Why use an override tree for a single board? do you intend to add variants?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31603 )
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
Patch Set 2:
(10 comments)
Looks interesting. My main concern is why the variant mechanism is used even when no variant is present.
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig File src/mainboard/asrock/h110m/Kconfig:
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig@5... PS2, Line 54: config MAINBOARD_FAMILY : string : default "ASROCK" : Is this used anywhere?
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig@6... PS2, Line 62: config DEVICETREE : string : default "variants/baseboard/devicetree.cb" : : config OVERRIDE_DEVICETREE : string : default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" This isn't needed if no variants are used.
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig@7... PS2, Line 73: "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.dvs.bin" Does this exist?
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Makefile.... File src/mainboard/asrock/h110m/Makefile.inc:
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Makefile.... PS2, Line 25: subdirs-y += variants/baseboard : CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include : : subdirs-y += variants/$(VARIANT_DIR) : CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include This can be removed if not using variants
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/cmos.defa... File src/mainboard/asrock/h110m/cmos.default:
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/cmos.defa... PS2, Line 2: Spew Please default to "Debug"
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/dsdt.asl File src/mainboard/asrock/h110m/dsdt.asl:
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/dsdt.asl@... PS2, Line 29: // Some generic macros This comment can be removed
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/spd/spd_u... File src/mainboard/asrock/h110m/spd/spd_util.c:
PS2: Is this needed?
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... File src/mainboard/asrock/h110m/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 54: register "SkipExtGfxScan" = "1" Um?
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 224: device pci 1c.0 off end # PCI Express Port 1 : device pci 1c.1 off end # PCI Express Port 2 : device pci 1c.2 off end # PCI Express Port 3 : device pci 1c.3 off end # PCI Express Port 4 : device pci 1c.4 off end # PCI Express Port 5 : device pci 1c.5 off end # PCI Express Port 6 : device pci 1c.6 off end # PCI Express Port 7 : device pci 1c.7 off end # PCI Express Port 8 : device pci 1d.0 off end # PCI Express Port 9 : device pci 1d.1 off end # PCI Express Port 10 : device pci 1d.2 off end # PCI Express Port 11 : device pci 1d.3 off end # PCI Express Port 12 How are PCIe ports working?
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... File src/mainboard/asrock/h110m/variants/dvs/overridetree.cb:
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 131: Why are these spaces?
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31603 )
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/spd/spd_u... File src/mainboard/asrock/h110m/spd/spd_util.c:
PS2:
Is this needed?
That only Intel can answer as it's undocumented. I'd leave it as it's board specific, but spd_util.c is a bad name. There's no SPD handling in here.
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... File src/mainboard/asrock/h110m/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 243: off Should always be on
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 246: off Set to on to enable onboard audio. You might need to configure gpios if not done already.
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31603 )
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/romstage.... File src/mainboard/asrock/h110m/romstage.c:
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/romstage.... PS2, Line 48: mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; Huh.. you cannot take pointers from the stackframe and assume their contents are still intact when you reference them later. Was this copied from somewhere else?
Move struct spd_block to .bss (aka declare as global static).
Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31603 )
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/romstage.... File src/mainboard/asrock/h110m/romstage.c:
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/romstage.... PS2, Line 48: mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3];
Huh.. […]
Ah, just ignore the comment. The referenced arrays are already in .bss.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31603 )
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
Patch Set 2: Code-Review+1
(8 comments)
Once this builds on Jenkins, it should be submitted, and other fixes done in follow-up commits.
https://review.coreboot.org/#/c/31603/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31603/2//COMMIT_MSG@9 PS2, Line 9: Kabylake Kaby Lake
https://review.coreboot.org/#/c/31603/2//COMMIT_MSG@11 PS2, Line 11: OS Maybe add *(Ubuntu 16.04.2 with Linux 4.15)* already here.
https://review.coreboot.org/#/c/31603/2//COMMIT_MSG@13 PS2, Line 13: Intel FSP2.0 I do not know much about that, but is there a revision or something similar?
https://review.coreboot.org/#/c/31603/2//COMMIT_MSG@16 PS2, Line 16: Work Works
https://review.coreboot.org/#/c/31603/2//COMMIT_MSG@17 PS2, Line 17: - Integrated graphics (only DVI port); What resolution did you use?
https://review.coreboot.org/#/c/31603/2//COMMIT_MSG@28 PS2, Line 28: Seabios SeaBIOS (what version)
https://review.coreboot.org/#/c/31603/2//COMMIT_MSG@28 PS2, Line 28: Tianocore TianoCore (what version)?
https://review.coreboot.org/#/c/31603/2//COMMIT_MSG@30 PS2, Line 30: What about suspend and resume?
Hello Angel Pons, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31603
to look at the new patch set (#3).
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
mainboard: Add ASRock H110M-DVS
This board is compatible with Intel Skylake and Kaby Lake generation processors. This patch contains the minimum configuration for booting and stable operation of the Ubuntu OS (18.04.1, Linux kernel 4.15). It is based on Intel RVP8 mainboard.
Intel Kaby Lake FSP 3.6.0 is used to initialize CPU and PCH. Graphics init with libgfxinit.
Works: - Integrated graphics (only DVI port, tested with 1920x1080); - PEG x16 (FSP must be configured with BCT to enable PEG); - all PCIe x1 slots; - all USB and SATA ports; - SuperIO COM port for console; - onboard audio.
TODO: - other SuperIO functions; - onboard network chip; - suspend and resume; - documentation.
Tested on Intel Core i5-6600 processor with Seabios (rel-1.12.0-10- g171fc89) and Tianocore/edk2 (vUDK2018-8-ge6eccfc) as a payload.
Change-Id: I69396edc50948cf1d0da649241ce92171d32daf7 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/mainboard/asrock/h110m/Kconfig A src/mainboard/asrock/h110m/Kconfig.name A src/mainboard/asrock/h110m/Makefile.inc A src/mainboard/asrock/h110m/acpi/dptf.asl A src/mainboard/asrock/h110m/acpi/ec.asl A src/mainboard/asrock/h110m/acpi/mainboard.asl A src/mainboard/asrock/h110m/acpi/superio.asl A src/mainboard/asrock/h110m/acpi_tables.c A src/mainboard/asrock/h110m/board_info.txt A src/mainboard/asrock/h110m/bootblock.c A src/mainboard/asrock/h110m/cmos.default A src/mainboard/asrock/h110m/cmos.layout A src/mainboard/asrock/h110m/data.vbt A src/mainboard/asrock/h110m/devicetree.cb A src/mainboard/asrock/h110m/dsdt.asl A src/mainboard/asrock/h110m/gma-mainboard.ads A src/mainboard/asrock/h110m/hda_verb.c A src/mainboard/asrock/h110m/include/gpio.h A src/mainboard/asrock/h110m/include/hda_verb.h A src/mainboard/asrock/h110m/mainboard.c A src/mainboard/asrock/h110m/ramstage.c A src/mainboard/asrock/h110m/romstage.c A src/mainboard/asrock/h110m/spd/Makefile.inc A src/mainboard/asrock/h110m/spd/spd.h A src/mainboard/asrock/h110m/spd/spd_util.c 25 files changed, 1,373 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31603/3
Hello Angel Pons, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31603
to look at the new patch set (#4).
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
mainboard: Add ASRock H110M-DVS
This board is compatible with Intel Skylake and Kaby Lake generation processors. This patch contains the minimum configuration for booting and stable operation of the Ubuntu OS (18.04.1, Linux kernel 4.15). It is based on Intel RVP8 mainboard.
Intel Kaby Lake FSP 3.6.0 is used to initialize CPU and PCH. Graphics init with libgfxinit.
Works: - Integrated graphics (only DVI port, tested with 1920x1080); - PEG x16 (FSP must be configured with BCT to enable PEG); - all PCIe x1 slots; - all USB and SATA ports; - SuperIO COM port for console; - onboard audio.
TODO: - other SuperIO functions; - onboard network chip; - suspend and resume; - documentation.
Tested on Intel Core i5-6600 processor with Seabios (rel-1.12.0-10- g171fc89) and Tianocore/edk2 (vUDK2018-8-ge6eccfc) as a payload.
Change-Id: I69396edc50948cf1d0da649241ce92171d32daf7 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/mainboard/asrock/h110m/Kconfig A src/mainboard/asrock/h110m/Kconfig.name A src/mainboard/asrock/h110m/Makefile.inc A src/mainboard/asrock/h110m/acpi/dptf.asl A src/mainboard/asrock/h110m/acpi/ec.asl A src/mainboard/asrock/h110m/acpi/mainboard.asl A src/mainboard/asrock/h110m/acpi/superio.asl A src/mainboard/asrock/h110m/acpi_tables.c A src/mainboard/asrock/h110m/board_info.txt A src/mainboard/asrock/h110m/bootblock.c A src/mainboard/asrock/h110m/cmos.default A src/mainboard/asrock/h110m/cmos.layout A src/mainboard/asrock/h110m/data.vbt A src/mainboard/asrock/h110m/devicetree.cb A src/mainboard/asrock/h110m/dsdt.asl A src/mainboard/asrock/h110m/gma-mainboard.ads A src/mainboard/asrock/h110m/hda_verb.c A src/mainboard/asrock/h110m/include/gpio.h A src/mainboard/asrock/h110m/include/hda_verb.h A src/mainboard/asrock/h110m/mainboard.c A src/mainboard/asrock/h110m/ramstage.c A src/mainboard/asrock/h110m/romstage.c A src/mainboard/asrock/h110m/spd/Makefile.inc A src/mainboard/asrock/h110m/spd/spd.h A src/mainboard/asrock/h110m/spd/spd_util.c 25 files changed, 1,372 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31603/4
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31603 )
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
Patch Set 4:
(21 comments)
Patch Set 2:
(10 comments)
Looks interesting. My main concern is why the variant mechanism is used even when no variant is present.
I reworked the patch to remove the "variants" directory. I`ll put it back in one of the following patches to add another motherboard from the "H110M" series.
https://review.coreboot.org/#/c/31603/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31603/2//COMMIT_MSG@9 PS2, Line 9: Kabylake
Kaby Lake
Done
https://review.coreboot.org/#/c/31603/2//COMMIT_MSG@11 PS2, Line 11: OS
Maybe add *(Ubuntu 16.04.2 with Linux 4.15)* already here.
Done
https://review.coreboot.org/#/c/31603/2//COMMIT_MSG@16 PS2, Line 16: Work
Works
Done
https://review.coreboot.org/#/c/31603/2//COMMIT_MSG@17 PS2, Line 17: - Integrated graphics (only DVI port);
What resolution did you use?
1920x1080 This is the maximum resolution of my display.
https://review.coreboot.org/#/c/31603/2//COMMIT_MSG@28 PS2, Line 28: Tianocore
TianoCore (what version)?
Done
https://review.coreboot.org/#/c/31603/2//COMMIT_MSG@28 PS2, Line 28: Seabios
SeaBIOS (what version)
Done
https://review.coreboot.org/#/c/31603/2//COMMIT_MSG@30 PS2, Line 30:
What about suspend and resume?
Sorry, I forgot to mention that this isn`t working. Board uses _PTS and _WAK ACPI-methods from https://github.com/coreboot/coreboot/blob/master/src/soc/intel/skylake/acpi/... I added it to dsdt.asl. When I do suspend in the OS, the system falls to sleep state, but after that it does not wake up.
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig File src/mainboard/asrock/h110m/Kconfig:
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig@1... PS2, Line 16: TSC_MONOTONIC_TIMER
already selected in the skylake soc Kconfig
Done
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig@2... PS2, Line 20: HAVE_SMI_HANDLER
already selected in the skylake soc Kconfig
Done
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig@2... PS2, Line 24: choice : prompt "Processor family" : default USE_SOC_INTEL_SKYLAKE : : config USE_SOC_INTEL_SKYLAKE : bool "Skylake" : select SOC_INTEL_SKYLAKE : : config USE_SOC_INTEL_KABYLAKE : bool "Kabylake" : select SOC_INTEL_KABYLAKE : : endchoice
is making this distinction really needed? you end up using the kabylake FSP anyway iirc.
Done
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig@5... PS2, Line 54: config MAINBOARD_FAMILY : string : default "ASROCK" :
Is this used anywhere?
Done
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig@6... PS2, Line 62: config DEVICETREE : string : default "variants/baseboard/devicetree.cb" : : config OVERRIDE_DEVICETREE : string : default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
This isn't needed if no variants are used.
I reworked the patch to remove the "variants" directory. I`ll put it back in one of the following patches to add another motherboard from the "H110M" series.
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig@7... PS2, Line 73: BOARD_ASROCK_H110M_DVS
not needed.
Done
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig@7... PS2, Line 73: "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.dvs.bin"
Does this exist?
I removed it
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig@7... PS2, Line 78: BOARD_ASROCK_H110M_DVS
not needed.
Done
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/cmos.defa... File src/mainboard/asrock/h110m/cmos.default:
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/cmos.defa... PS2, Line 2: Spew
Please default to "Debug"
Done
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... File src/mainboard/asrock/h110m/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 38: # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f : register "gen1_dec" = "0x00fc0801
I don't see a device decoding this range.
I removed it
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 54: register "SkipExtGfxScan" = "1"
Um?
Yes, I think it will be true if "SkipExtGfxScan" is set to 0 so that the system would scan external graphics. However, the external GPU works without it.
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 156: register "pirqa_routing" = "0x0b" : register "pirqb_routing" = "0x0a" : register "pirqc_routing" = "0x0b" : register "pirqd_routing" = "0x0b" : register "pirqe_routing" = "0x0b" : register "pirqf_routing" = "0x0b" : register "pirqg_routing" = "0x0b" : register "pirqh_routing" = "0x0b"
already done at line 60.
I removed it
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 224: device pci 1c.0 off end # PCI Express Port 1 : device pci 1c.1 off end # PCI Express Port 2 : device pci 1c.2 off end # PCI Express Port 3 : device pci 1c.3 off end # PCI Express Port 4 : device pci 1c.4 off end # PCI Express Port 5 : device pci 1c.5 off end # PCI Express Port 6 : device pci 1c.6 off end # PCI Express Port 7 : device pci 1c.7 off end # PCI Express Port 8 : device pci 1d.0 off end # PCI Express Port 9 : device pci 1d.1 off end # PCI Express Port 10 : device pci 1d.2 off end # PCI Express Port 11 : device pci 1d.3 off end # PCI Express Port 12
How are PCIe ports working?
I used to enable ports in overridetree.cb, but then I decided to move it to devicetree until new version of this board is added to project.
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 246: off
Set to on to enable onboard audio. […]
I enabled hda need to add "EnableAzalia" = "1"
Hello Angel Pons, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31603
to look at the new patch set (#5).
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
mainboard: Add ASRock H110M-DVS
This board is compatible with Intel Skylake and Kaby Lake generation processors. This patch contains the minimum configuration for booting and stable operation of the Ubuntu OS (18.04.1, Linux kernel 4.15). It is based on Intel RVP8 mainboard.
Intel Kaby Lake FSP 3.6.0 is used to initialize CPU and PCH. Graphics init with libgfxinit.
Works: - Integrated graphics (only DVI port, tested with 1920x1080); - PEG x16 (FSP must be configured with BCT to enable PEG); - all PCIe x1 slots; - all USB and SATA ports; - SuperIO COM port for console; - onboard audio.
TODO: - other SuperIO functions; - onboard network chip; - suspend and resume; - documentation.
Tested on Intel Core i5-6600 processor with Seabios (rel-1.12.0-10- g171fc89) and Tianocore/edk2 (vUDK2018-8-ge6eccfc) as a payload.
Change-Id: I69396edc50948cf1d0da649241ce92171d32daf7 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/mainboard/asrock/h110m/Kconfig A src/mainboard/asrock/h110m/Kconfig.name A src/mainboard/asrock/h110m/Makefile.inc A src/mainboard/asrock/h110m/acpi/dptf.asl A src/mainboard/asrock/h110m/acpi/ec.asl A src/mainboard/asrock/h110m/acpi/mainboard.asl A src/mainboard/asrock/h110m/acpi/superio.asl A src/mainboard/asrock/h110m/acpi_tables.c A src/mainboard/asrock/h110m/board_info.txt A src/mainboard/asrock/h110m/bootblock.c A src/mainboard/asrock/h110m/cmos.default A src/mainboard/asrock/h110m/cmos.layout A src/mainboard/asrock/h110m/data.vbt A src/mainboard/asrock/h110m/devicetree.cb A src/mainboard/asrock/h110m/dsdt.asl A src/mainboard/asrock/h110m/gma-mainboard.ads A src/mainboard/asrock/h110m/hda_verb.c A src/mainboard/asrock/h110m/include/gpio.h A src/mainboard/asrock/h110m/include/hda_verb.h A src/mainboard/asrock/h110m/mainboard.c A src/mainboard/asrock/h110m/ramstage.c A src/mainboard/asrock/h110m/romstage.c A src/mainboard/asrock/h110m/spd/Makefile.inc A src/mainboard/asrock/h110m/spd/spd.h A src/mainboard/asrock/h110m/spd/spd_util.c 25 files changed, 1,372 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31603/5
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31603 )
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
Patch Set 5: Code-Review+1
(2 comments)
https://review.coreboot.org/#/c/31603/5/src/mainboard/asrock/h110m/include/h... File src/mainboard/asrock/h110m/include/hda_verb.h:
https://review.coreboot.org/#/c/31603/5/src/mainboard/asrock/h110m/include/h... PS5, Line 4: * Copyright (C) 2017 Intel Corporation if you don't use variants, the file contents can be moved to hda_verb.c
https://review.coreboot.org/#/c/31603/5/src/mainboard/asrock/h110m/spd/spd_u... File src/mainboard/asrock/h110m/spd/spd_util.c:
https://review.coreboot.org/#/c/31603/5/src/mainboard/asrock/h110m/spd/spd_u... PS5, Line 4: * Copyright (C) 2016 Intel Corporation. move everything to romstage.c and make it static there's no need for additonal files
Hello Angel Pons, Patrick Rudolph, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31603
to look at the new patch set (#6).
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
mainboard: Add ASRock H110M-DVS
This board is compatible with Intel Skylake and Kaby Lake generation processors. This patch contains the minimum configuration for booting and stable operation of the Ubuntu OS (18.04.1, Linux kernel 4.15). It is based on Intel RVP8 mainboard.
Intel Kaby Lake FSP 3.6.0 is used to initialize CPU and PCH. Graphics init with libgfxinit.
Works: - Integrated graphics (only DVI port, tested with 1920x1080); - PEG x16 (FSP must be configured with BCT to enable PEG); - all PCIe x1 slots; - all USB and SATA ports; - SuperIO COM port for console; - onboard audio.
TODO: - other SuperIO functions; - onboard network chip; - suspend and resume; - documentation.
Tested on Intel Core i5-6600 processor with Seabios (rel-1.12.0-10- g171fc89) and Tianocore/edk2 (vUDK2018-8-ge6eccfc) as a payload.
Change-Id: I69396edc50948cf1d0da649241ce92171d32daf7 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/mainboard/asrock/h110m/Kconfig A src/mainboard/asrock/h110m/Kconfig.name A src/mainboard/asrock/h110m/Makefile.inc A src/mainboard/asrock/h110m/acpi/dptf.asl A src/mainboard/asrock/h110m/acpi/ec.asl A src/mainboard/asrock/h110m/acpi/mainboard.asl A src/mainboard/asrock/h110m/acpi/superio.asl A src/mainboard/asrock/h110m/acpi_tables.c A src/mainboard/asrock/h110m/board_info.txt A src/mainboard/asrock/h110m/bootblock.c A src/mainboard/asrock/h110m/cmos.default A src/mainboard/asrock/h110m/cmos.layout A src/mainboard/asrock/h110m/data.vbt A src/mainboard/asrock/h110m/devicetree.cb A src/mainboard/asrock/h110m/dsdt.asl A src/mainboard/asrock/h110m/gma-mainboard.ads A src/mainboard/asrock/h110m/hda_verb.c A src/mainboard/asrock/h110m/include/gpio.h A src/mainboard/asrock/h110m/mainboard.c A src/mainboard/asrock/h110m/ramstage.c A src/mainboard/asrock/h110m/romstage.c 21 files changed, 1,276 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31603/6
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31603 )
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
Patch Set 6: Code-Review+1
Hello Patrick Rudolph, Angel Pons, Patrick Rudolph, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31603
to look at the new patch set (#7).
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
mainboard: Add ASRock H110M-DVS
This board is compatible with Intel Skylake and Kaby Lake generation processors. This patch contains the minimum configuration for booting and stable operation of the Ubuntu OS (18.04.1, Linux kernel 4.15). It is based on Intel RVP8 mainboard.
Intel Kaby Lake FSP 3.6.0 is used to initialize CPU and PCH. Graphics init with libgfxinit.
Works: - Integrated graphics (only DVI port, tested with 1920x1080); - PEG x16 (FSP must be configured with BCT to enable PEG); - all PCIe x1 slots; - all USB and SATA ports; - SuperIO COM port for console; - onboard audio.
TODO: - other SuperIO functions; - onboard network chip; - suspend and resume; - documentation.
Tested on Intel Core i5-6600 processor with Seabios (rel-1.12.0-10- g171fc89) and Tianocore/edk2 (vUDK2018-8-ge6eccfc) as a payload.
Change-Id: I69396edc50948cf1d0da649241ce92171d32daf7 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A src/mainboard/asrock/h110m/Kconfig A src/mainboard/asrock/h110m/Kconfig.name A src/mainboard/asrock/h110m/Makefile.inc A src/mainboard/asrock/h110m/acpi/dptf.asl A src/mainboard/asrock/h110m/acpi/ec.asl A src/mainboard/asrock/h110m/acpi/mainboard.asl A src/mainboard/asrock/h110m/acpi/superio.asl A src/mainboard/asrock/h110m/acpi_tables.c A src/mainboard/asrock/h110m/board_info.txt A src/mainboard/asrock/h110m/bootblock.c A src/mainboard/asrock/h110m/cmos.default A src/mainboard/asrock/h110m/cmos.layout A src/mainboard/asrock/h110m/data.vbt A src/mainboard/asrock/h110m/devicetree.cb A src/mainboard/asrock/h110m/dsdt.asl A src/mainboard/asrock/h110m/gma-mainboard.ads A src/mainboard/asrock/h110m/hda_verb.c A src/mainboard/asrock/h110m/include/gpio.h A src/mainboard/asrock/h110m/mainboard.c A src/mainboard/asrock/h110m/ramstage.c A src/mainboard/asrock/h110m/romstage.c 21 files changed, 1,276 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31603/7
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31603 )
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
Patch Set 7:
(13 comments)
Hi all! I'm sorry, maybe I did not understand, Review completed? I just started committing here recently and may not know all rules. I fixed everything. Do you have any notes on my patch?
I can add to my work a coreboot-log for this board:
https://drive.yadro.com/s/QmHGXD2gFDaPqT5
Regards, Maxim Polyakov
https://review.coreboot.org/#/c/31603/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31603/2//COMMIT_MSG@13 PS2, Line 13: Intel FSP2.0
I do not know much about that, but is there a revision or something similar?
In Intel FSP repository it has Specification Version 2.0 * from https://github.com/IntelFsp/FSP :
|========================================|===================|===============| | | | FSP | | FSP Project Name | Directory Name | Specification | | | | Version | |========================================|===================|===============| | 7th Generation Intel® Core™ processors | KabylakeFspBinPkg | v2.0 * | | and chipsets (formerly Kaby Lake) | | | |========================================|===================|===============|
But in addition to this, FSP has revision 3.6.0 . I saw this revision in the last commit in the "Kabelake" branch: https://github.com/IntelFsp/FSP/commit/324ffc02523bf23a907a3ff305b43b5047adf...
I added "FSP 3.6.0" to the commit message.
https://review.coreboot.org/#/c/31603/2//COMMIT_MSG@17 PS2, Line 17: - Integrated graphics (only DVI port);
1920x1080 […]
I added this information to the commit message.
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig File src/mainboard/asrock/h110m/Kconfig:
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig@4... PS2, Line 45: : config VARIANT_DIR : string : default "dvs" if BOARD_ASROCK_H110M_DVS
remove until you add variants.
Done
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig@6... PS2, Line 62: config DEVICETREE : string : default "variants/baseboard/devicetree.cb" : : config OVERRIDE_DEVICETREE : string : default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
I reworked the patch to remove the "variants" directory. […]
Done
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/Kconfig@7... PS2, Line 73: "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/descriptor.dvs.bin"
I removed it
Done
https://review.coreboot.org/#/c/31603/5/src/mainboard/asrock/h110m/include/h... File src/mainboard/asrock/h110m/include/hda_verb.h:
https://review.coreboot.org/#/c/31603/5/src/mainboard/asrock/h110m/include/h... PS5, Line 4: * Copyright (C) 2017 Intel Corporation
if you don't use variants, the file contents can be moved to hda_verb. […]
Done
https://review.coreboot.org/#/c/31603/5/src/mainboard/asrock/h110m/spd/spd_u... File src/mainboard/asrock/h110m/spd/spd_util.c:
https://review.coreboot.org/#/c/31603/5/src/mainboard/asrock/h110m/spd/spd_u... PS5, Line 4: * Copyright (C) 2016 Intel Corporation.
move everything to romstage.c and make it static […]
Done
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... File src/mainboard/asrock/h110m/variants/baseboard/devicetree.cb:
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 38: # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f : register "gen1_dec" = "0x00fc0801
I removed it
Done
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 54: register "SkipExtGfxScan" = "1"
Yes, I think it will be true if "SkipExtGfxScan" is set to 0 so that the system would scan external […]
Done
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 156: register "pirqa_routing" = "0x0b" : register "pirqb_routing" = "0x0a" : register "pirqc_routing" = "0x0b" : register "pirqd_routing" = "0x0b" : register "pirqe_routing" = "0x0b" : register "pirqf_routing" = "0x0b" : register "pirqg_routing" = "0x0b" : register "pirqh_routing" = "0x0b"
I removed it
Done
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 224: device pci 1c.0 off end # PCI Express Port 1 : device pci 1c.1 off end # PCI Express Port 2 : device pci 1c.2 off end # PCI Express Port 3 : device pci 1c.3 off end # PCI Express Port 4 : device pci 1c.4 off end # PCI Express Port 5 : device pci 1c.5 off end # PCI Express Port 6 : device pci 1c.6 off end # PCI Express Port 7 : device pci 1c.7 off end # PCI Express Port 8 : device pci 1d.0 off end # PCI Express Port 9 : device pci 1d.1 off end # PCI Express Port 10 : device pci 1d.2 off end # PCI Express Port 11 : device pci 1d.3 off end # PCI Express Port 12
I used to enable ports in overridetree. […]
Done
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 243: off
Should always be on
Done
https://review.coreboot.org/#/c/31603/2/src/mainboard/asrock/h110m/variants/... PS2, Line 246: off
I enabled hda […]
Done
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31603 )
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
Patch Set 7:
Documentation is still missing.
Hello Patrick Rudolph, Angel Pons, Patrick Rudolph, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31603
to look at the new patch set (#8).
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
mainboard: Add ASRock H110M-DVS
This board is compatible with Intel Skylake and Kaby Lake generation processors. This patch contains the minimum configuration for booting and stable operation of the Ubuntu OS (18.04.1, Linux kernel 4.15). It is based on Intel RVP8 mainboard.
Intel Kaby Lake FSP 3.6.0 is used to initialize CPU and PCH. Graphics init with libgfxinit.
Works: - Integrated graphics (only DVI port, tested with 1920x1080); - PEG x16 (FSP must be configured with BCT to enable PEG); - all PCIe x1 slots; - all USB and SATA ports; - SuperIO COM port for console; - onboard audio.
TODO: - other SuperIO functions; - onboard network chip; - suspend and resume; - documentation.
Tested on Intel Core i5-6600 processor with Seabios (rel-1.12.0-10- g171fc89) and Tianocore/edk2 (vUDK2018-8-ge6eccfc) as a payload.
Change-Id: I69396edc50948cf1d0da649241ce92171d32daf7 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A Documentation/mainboard/asrock/h110m-dvs.md A src/mainboard/asrock/h110m/Kconfig A src/mainboard/asrock/h110m/Kconfig.name A src/mainboard/asrock/h110m/Makefile.inc A src/mainboard/asrock/h110m/acpi/dptf.asl A src/mainboard/asrock/h110m/acpi/ec.asl A src/mainboard/asrock/h110m/acpi/mainboard.asl A src/mainboard/asrock/h110m/acpi/superio.asl A src/mainboard/asrock/h110m/acpi_tables.c A src/mainboard/asrock/h110m/board_info.txt A src/mainboard/asrock/h110m/bootblock.c A src/mainboard/asrock/h110m/cmos.default A src/mainboard/asrock/h110m/cmos.layout A src/mainboard/asrock/h110m/data.vbt A src/mainboard/asrock/h110m/devicetree.cb A src/mainboard/asrock/h110m/dsdt.asl A src/mainboard/asrock/h110m/gma-mainboard.ads A src/mainboard/asrock/h110m/hda_verb.c A src/mainboard/asrock/h110m/include/gpio.h A src/mainboard/asrock/h110m/mainboard.c A src/mainboard/asrock/h110m/ramstage.c A src/mainboard/asrock/h110m/romstage.c 22 files changed, 1,450 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31603/8
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31603 )
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
Patch Set 8:
(5 comments)
Please reference the h110m-dvs.md from index.md, too.
https://review.coreboot.org/#/c/31603/8/Documentation/mainboard/asrock/h110m... File Documentation/mainboard/asrock/h110m-dvs.md:
https://review.coreboot.org/#/c/31603/8/Documentation/mainboard/asrock/h110m... PS8, Line 8: Intel company provides Firmware Support Package (2.0) ([intel FSP 2.0]) not a valid markdown link
https://review.coreboot.org/#/c/31603/8/Documentation/mainboard/asrock/h110m... PS8, Line 13: :doc:`../../soc/intel/code_development_model/code_development_model.md`. not a valid link. Since recommonmark 0.5 you can use regular markdown links.
https://review.coreboot.org/#/c/31603/8/Documentation/mainboard/asrock/h110m... PS8, Line 32: parameters in FSP.fd to initialize the PEG x16 port: it would be great if you could add support for setting these at runtime in a different commit
https://review.coreboot.org/#/c/31603/8/Documentation/mainboard/asrock/h110m... PS8, Line 34: Peg0Enable = Enable not a block in markdown
https://review.coreboot.org/#/c/31603/8/Documentation/mainboard/asrock/h110m... PS8, Line 92: sudo flashrom -p internal --ifd -i bios --noverify-all -w coreboot.rom that's already covered by the common flashing guide
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31603 )
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
Patch Set 10:
(5 comments)
Patch Set 8:
(5 comments)
Please reference the h110m-dvs.md from index.md, too.
Ok
https://review.coreboot.org/#/c/31603/8/Documentation/mainboard/asrock/h110m... File Documentation/mainboard/asrock/h110m-dvs.md:
https://review.coreboot.org/#/c/31603/8/Documentation/mainboard/asrock/h110m... PS8, Line 8: Intel company provides Firmware Support Package (2.0) ([intel FSP 2.0])
not a valid markdown link
Fixed
https://review.coreboot.org/#/c/31603/8/Documentation/mainboard/asrock/h110m... PS8, Line 13: :doc:`../../soc/intel/code_development_model/code_development_model.md`.
not a valid link. […]
Fixed
https://review.coreboot.org/#/c/31603/8/Documentation/mainboard/asrock/h110m... PS8, Line 32: parameters in FSP.fd to initialize the PEG x16 port:
it would be great if you could add support for setting these at runtime in a different commit
Yes, I would make this in one of the next patches.
https://review.coreboot.org/#/c/31603/8/Documentation/mainboard/asrock/h110m... PS8, Line 34: Peg0Enable = Enable
not a block in markdown
Fixed
https://review.coreboot.org/#/c/31603/8/Documentation/mainboard/asrock/h110m... PS8, Line 92: sudo flashrom -p internal --ifd -i bios --noverify-all -w coreboot.rom
that's already covered by the common flashing guide
Done
Hello Patrick Rudolph, Angel Pons, Patrick Rudolph, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31603
to look at the new patch set (#11).
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
mainboard: Add ASRock H110M-DVS
This board is compatible with Intel Skylake and Kaby Lake generation processors. This patch contains the minimum configuration for booting and stable operation of the Ubuntu OS (18.04.1, Linux kernel 4.15). It is based on Intel RVP8 mainboard.
Intel Kaby Lake FSP 3.6.0 is used to initialize CPU and PCH. Graphics init with libgfxinit.
Works: - Integrated graphics (only DVI port, tested with 1920x1080); - PEG x16 (FSP must be configured with BCT to enable PEG); - all PCIe x1 slots; - all USB and SATA ports; - SuperIO COM port for console; - onboard audio.
TODO: - other SuperIO functions; - onboard network chip; - suspend and resume; - documentation.
Tested on Intel Core i5-6600 processor with Seabios (rel-1.12.0-10- g171fc89) and Tianocore/edk2 (vUDK2018-8-ge6eccfc) as a payload.
Change-Id: I69396edc50948cf1d0da649241ce92171d32daf7 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A Documentation/mainboard/asrock/h110m-dvs.md M Documentation/mainboard/index.md A src/mainboard/asrock/h110m/Kconfig A src/mainboard/asrock/h110m/Kconfig.name A src/mainboard/asrock/h110m/Makefile.inc A src/mainboard/asrock/h110m/acpi/dptf.asl A src/mainboard/asrock/h110m/acpi/ec.asl A src/mainboard/asrock/h110m/acpi/mainboard.asl A src/mainboard/asrock/h110m/acpi/superio.asl A src/mainboard/asrock/h110m/acpi_tables.c A src/mainboard/asrock/h110m/board_info.txt A src/mainboard/asrock/h110m/bootblock.c A src/mainboard/asrock/h110m/cmos.default A src/mainboard/asrock/h110m/cmos.layout A src/mainboard/asrock/h110m/data.vbt A src/mainboard/asrock/h110m/devicetree.cb A src/mainboard/asrock/h110m/dsdt.asl A src/mainboard/asrock/h110m/gma-mainboard.ads A src/mainboard/asrock/h110m/hda_verb.c A src/mainboard/asrock/h110m/include/gpio.h A src/mainboard/asrock/h110m/mainboard.c A src/mainboard/asrock/h110m/ramstage.c A src/mainboard/asrock/h110m/romstage.c 23 files changed, 1,434 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31603/11
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31603 )
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
Patch Set 12:
Hi all! I fixed the errors in the documentation.
In addition to this, I rebased my patch and reworked the Serial IRQ configuration for this board using changes from commit: "soc/intel/skylake: Unify serial IRQ options" Change-Id: I79f0cd302e335d8dcf8bf6bc32f3d40ca6713e5c
Are there any other notes regarding my patch? Thank. Regards, Maxim Polyakov
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31603 )
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/#/c/31603/8/Documentation/mainboard/asrock/h110m... File Documentation/mainboard/asrock/h110m-dvs.md:
https://review.coreboot.org/#/c/31603/8/Documentation/mainboard/asrock/h110m... PS8, Line 32: parameters in FSP.fd to initialize the PEG x16 port:
Yes, I would make this in one of the next patches.
Done in the next patch: Change-Id: Ia4f29df47d76de5069fe53120434cc7c2ab6f044
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31603 )
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
Patch Set 12:
(4 comments)
https://review.coreboot.org/#/c/31603/12/Documentation/mainboard/asrock/h110... File Documentation/mainboard/asrock/h110m-dvs.md:
https://review.coreboot.org/#/c/31603/12/Documentation/mainboard/asrock/h110... PS12, Line 8: Intel company provides [Firmware Support Package (2.0)](Documentation/soc/intel/fsp/index.md) ../../Documentation/
https://review.coreboot.org/#/c/31603/12/Documentation/mainboard/asrock/h110... PS12, Line 10: [document](Documentation/soc/intel/code_development_model/code_development_model.md). ../../Documentation/
https://review.coreboot.org/#/c/31603/12/Documentation/mainboard/asrock/h110... PS12, Line 30: ```eval_rst that's not RST code. Use ``` for block quote
https://review.coreboot.org/#/c/31603/12/Documentation/mainboard/asrock/h110... PS12, Line 31: Peg0Enable = Enable no need for whitespace at beginning of line
Hello Patrick Rudolph, Angel Pons, Patrick Rudolph, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31603
to look at the new patch set (#13).
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
mainboard: Add ASRock H110M-DVS
This board is compatible with Intel Skylake and Kaby Lake generation processors. This patch contains the minimum configuration for booting and stable operation of the Ubuntu OS (18.04.1, Linux kernel 4.15). It is based on Intel RVP8 mainboard.
Intel Kaby Lake FSP 3.6.0 is used to initialize CPU and PCH. Graphics init with libgfxinit.
Works: - Integrated graphics (only DVI port, tested with 1920x1080); - PEG x16 (FSP must be configured with BCT to enable PEG); - all PCIe x1 slots; - all USB and SATA ports; - SuperIO COM port for console; - onboard audio.
TODO: - other SuperIO functions; - onboard network chip; - suspend and resume; - documentation.
Tested on Intel Core i5-6600 processor with Seabios (rel-1.12.0-10- g171fc89) and Tianocore/edk2 (vUDK2018-8-ge6eccfc) as a payload.
Change-Id: I69396edc50948cf1d0da649241ce92171d32daf7 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- A Documentation/mainboard/asrock/h110m-dvs.md M Documentation/mainboard/index.md A src/mainboard/asrock/h110m/Kconfig A src/mainboard/asrock/h110m/Kconfig.name A src/mainboard/asrock/h110m/Makefile.inc A src/mainboard/asrock/h110m/acpi/dptf.asl A src/mainboard/asrock/h110m/acpi/ec.asl A src/mainboard/asrock/h110m/acpi/mainboard.asl A src/mainboard/asrock/h110m/acpi/superio.asl A src/mainboard/asrock/h110m/acpi_tables.c A src/mainboard/asrock/h110m/board_info.txt A src/mainboard/asrock/h110m/bootblock.c A src/mainboard/asrock/h110m/cmos.default A src/mainboard/asrock/h110m/cmos.layout A src/mainboard/asrock/h110m/data.vbt A src/mainboard/asrock/h110m/devicetree.cb A src/mainboard/asrock/h110m/dsdt.asl A src/mainboard/asrock/h110m/gma-mainboard.ads A src/mainboard/asrock/h110m/hda_verb.c A src/mainboard/asrock/h110m/include/gpio.h A src/mainboard/asrock/h110m/mainboard.c A src/mainboard/asrock/h110m/ramstage.c A src/mainboard/asrock/h110m/romstage.c 23 files changed, 1,434 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31603/13
Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31603 )
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
Patch Set 13:
(4 comments)
https://review.coreboot.org/#/c/31603/12/Documentation/mainboard/asrock/h110... File Documentation/mainboard/asrock/h110m-dvs.md:
https://review.coreboot.org/#/c/31603/12/Documentation/mainboard/asrock/h110... PS12, Line 8: Intel company provides [Firmware Support Package (2.0)](Documentation/soc/intel/fsp/index.md)
../.. […]
Done
https://review.coreboot.org/#/c/31603/12/Documentation/mainboard/asrock/h110... PS12, Line 10: [document](Documentation/soc/intel/code_development_model/code_development_model.md).
../.. […]
Done
https://review.coreboot.org/#/c/31603/12/Documentation/mainboard/asrock/h110... PS12, Line 30: ```eval_rst
that's not RST code. […]
Done
https://review.coreboot.org/#/c/31603/12/Documentation/mainboard/asrock/h110... PS12, Line 31: Peg0Enable = Enable
no need for whitespace at beginning of line
Done
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31603 )
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
Patch Set 13: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31603 )
Change subject: mainboard: Add ASRock H110M-DVS ......................................................................
mainboard: Add ASRock H110M-DVS
This board is compatible with Intel Skylake and Kaby Lake generation processors. This patch contains the minimum configuration for booting and stable operation of the Ubuntu OS (18.04.1, Linux kernel 4.15). It is based on Intel RVP8 mainboard.
Intel Kaby Lake FSP 3.6.0 is used to initialize CPU and PCH. Graphics init with libgfxinit.
Works: - Integrated graphics (only DVI port, tested with 1920x1080); - PEG x16 (FSP must be configured with BCT to enable PEG); - all PCIe x1 slots; - all USB and SATA ports; - SuperIO COM port for console; - onboard audio.
TODO: - other SuperIO functions; - onboard network chip; - suspend and resume; - documentation.
Tested on Intel Core i5-6600 processor with Seabios (rel-1.12.0-10- g171fc89) and Tianocore/edk2 (vUDK2018-8-ge6eccfc) as a payload.
Change-Id: I69396edc50948cf1d0da649241ce92171d32daf7 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/31603 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org --- A Documentation/mainboard/asrock/h110m-dvs.md M Documentation/mainboard/index.md A src/mainboard/asrock/h110m/Kconfig A src/mainboard/asrock/h110m/Kconfig.name A src/mainboard/asrock/h110m/Makefile.inc A src/mainboard/asrock/h110m/acpi/dptf.asl A src/mainboard/asrock/h110m/acpi/ec.asl A src/mainboard/asrock/h110m/acpi/mainboard.asl A src/mainboard/asrock/h110m/acpi/superio.asl A src/mainboard/asrock/h110m/acpi_tables.c A src/mainboard/asrock/h110m/board_info.txt A src/mainboard/asrock/h110m/bootblock.c A src/mainboard/asrock/h110m/cmos.default A src/mainboard/asrock/h110m/cmos.layout A src/mainboard/asrock/h110m/data.vbt A src/mainboard/asrock/h110m/devicetree.cb A src/mainboard/asrock/h110m/dsdt.asl A src/mainboard/asrock/h110m/gma-mainboard.ads A src/mainboard/asrock/h110m/hda_verb.c A src/mainboard/asrock/h110m/include/gpio.h A src/mainboard/asrock/h110m/mainboard.c A src/mainboard/asrock/h110m/ramstage.c A src/mainboard/asrock/h110m/romstage.c 23 files changed, 1,434 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/Documentation/mainboard/asrock/h110m-dvs.md b/Documentation/mainboard/asrock/h110m-dvs.md new file mode 100644 index 0000000..614669b --- /dev/null +++ b/Documentation/mainboard/asrock/h110m-dvs.md @@ -0,0 +1,162 @@ +# ASRock H110M-DVS + +This page describes how to run coreboot on the [ASRock H110M-DVS]. + +## Required proprietary blobs + +Mainboard is based on Intel Skylake/Kaby Lake processor and H110 Chipset. +Intel company provides [Firmware Support Package (2.0)](../../Documentation/soc/intel/fsp/index.md) +(intel FSP 2.0) to initialize this generation silicon. Please see this +[document](../../Documentation/soc/intel/code_development_model/code_development_model.md). + +FSP Information: + +```eval_rst ++-----------------------------+-------------------+-------------------+ +| FSP Project Name | Directory | Specification | ++-----------------------------+-------------------+-------------------+ +| 7th Generation Intel® Core™ | KabylakeFspBinPkg | 2.0 | +| processors and chipsets | | | +| (formerly Kaby Lake) | | | ++-----------------------------+-------------------+-------------------+ +``` + +Please take FSP from the directory `3rdparty/fsp/KabylakeFspBinPkg/` in +the coreboot or download the latest version from [github][FSP github]. + +You must use [Intel Binary Configuration Tool] BCT to set the following +parameters in FSP.fd to initialize the PEG x16 port: + +``` +Peg0Enable = Enable +Peg0MaxLinkSpeed = Gen3 +Peg0MaxLinkWidth = Auto +``` + +BCT creates Fsp_M.fd, Fsp_S.fd and Fsp_T.fd. These files are integrated +into the coreboot image. If PEG port is not used, you can get these files +without BTC: + +```bash +# split FSP.fd +python 3rdparty/fsp/Tools/SplitFspBin.py split -f 3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd +``` + +## Building coreboot + +The following steps set the default parameters for this board to build a +fully working image: + +```bash +make distclean +touch .config +./util/scripts/config --enable VENDOR_ASROCK +./util/scripts/config --enable BOARD_ASROCK_H110M_DVS +./util/scripts/config --enable CONFIG_ADD_FSP_BINARIES +./util/scripts/config --set-str CONFIG_FSP_M_FILE "/path/to/Fsp_M.fd" +./util/scripts/config --set-str CONFIG_FSP_S_FILE "/path/to/Fsp_S.fd" +./util/scripts/config --set-str REALTEK_8168_MACADDRESS "xx:xx:xx:xx:xx:xx" +make olddefconfig +``` + +However, it is strongly advised to use `make menuconfig` afterwards +(or instead), so that you can see all of the settings. + +Use the following command to disable the serial console if debugging +output is not required: + +```bash +./util/scripts/config --disable CONSOLE_SERIAL +``` + +However, a more flexible method is to change the console log level from +within an OS using `util/nvramtool`, or with the `nvramcui` payload. + +Now, run `make` to build the coreboot image. + +## Flashing coreboot + +### Internal programming + +The main SPI flash can be accessed using [flashrom]. By default, only +the BIOS region of the flash is writable. If you wish to change any +other region, such as the Management Engine or firmware descriptor, then +an external programmer is required (unless you find a clever way around +the flash protection). More information about this [here](../../Documentation/flash_tutorial/index.md). + +### External programming + +The flash chip is a 8 MiB socketed DIP-8 chip. Specifically, it's a +Macronix MX25L6473E, whose datasheet can be found [here][MX25L6473E]. +The chip is located to the bottom right-hand side of the board. For +a precise location, refer to section 1.3 (Motherboard Layout) of the +[H110M-DVS manual], where the chip is labelled "64Mb BIOS". Take note of +the chip's orientation, remove it from its socket, and flash it with +an external programmer. For reference, the notch in the chip should be +facing towards the bottom of the board. + +## Known issues + +- The VGA port doesn't work. + +- PEG x16 port training correctly runs only at link speed of 2.5GT/s(gen1). + It takes more time to research the schematic of this board. + +- SuperIO GPIO pin is used to reset Realtek chip. However, since the + Logical Device 7 (GPIO6, GPIO7, GPIO8) is not initialized, the network + chip is in a reset state all the time. + +## Untested + +- parallel port +- PS/2 keyboard +- PS/2 mouse +- EHCI debug +- TPM +- infrared module +- chassis intrusion header +- chassis speaker header + +## Working + +- integrated graphics init with libgfxinit (see [Known issues](#known-issues)) +- PCIe x1 +- PEG x16 Gen1 (see [Known issues](#known-issues)) +- SATA +- USB +- serial port +- onboard audio +- using `me_cleaner` +- using `flashrom` + +## TODO + +- PEG x16 Gen3 +- NCT6791D GPIOs +- onboard network (see [Known issues](#known-issues)) +- S3 suspend/resume +- Wake-on-LAN +- hardware monitor + +## Technology + +```eval_rst ++------------------+--------------------------------------------------+ +| CPU | Intel Skylake/Kaby Lake (LGA1151) | ++------------------+--------------------------------------------------+ +| PCH | Intel Sunrise Point H110 | ++------------------+--------------------------------------------------+ +| Super I/O | Nuvoton NCT6791D | ++------------------+--------------------------------------------------+ +| EC | None | ++------------------+--------------------------------------------------+ +| Coprocessor | Intel Management Engine | ++------------------+--------------------------------------------------+ +``` + +[ASRock H110M-DVS]: https://www.asrock.com/mb/Intel/H110M-DVS%20R2.0/ +[FSP github]: https://github.com/IntelFsp/FSP +[Intel Binary Configuration Tool]: https://github.com/IntelFsp/BCT +[MX25L6473E]: http://www.macronix.com/Lists/Datasheet/Attachments/7380/MX25L6473E,%203V,%2... +[flashrom]: https://flashrom.org/Flashrom +[H110M-DVS manual]: http://asrock.pc.cdn.bitgravity.com/Manual/H110M-DVS%20R2.0.pdf diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 56adb25..d94c23e 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -10,6 +10,7 @@ ## ASRock
- [H81M-HDS](asrock/h81m-hds.md) +- [H110M-DVS](asrock/h110m-dvs.md)
## Cavium
diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig new file mode 100644 index 0000000..3d21113 --- /dev/null +++ b/src/mainboard/asrock/h110m/Kconfig @@ -0,0 +1,54 @@ +if BOARD_ASROCK_H110M_DVS + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select INTEL_GMA_HAVE_VBT + select INTEL_INT15 + select SOC_INTEL_KABYLAKE + select SKYLAKE_SOC_PCH_H + select MAINBOARD_USES_FSP2_0 + select GENERIC_SPD_BIN + select SUPERIO_NUVOTON_NCT6791D + select SUPERIO_NUVOTON_NCT6776_COM_A + select REALTEK_8168_RESET + select RT8168_SET_LED_MODE + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "asrock/h110m" + +config MAINBOARD_PART_NUMBER + string + default "H110M" + +config MAX_CPUS + int + default 8 + +config DEVICETREE + string + default "devicetree.cb" + +config PRERAM_CBMEM_CONSOLE_SIZE + hex + default 0xd00 + +config DIMM_SPD_SIZE + int + default 512 #DDR4 + +# This is overridden if CMOS is used for configuration values. +config MAINBOARD_POWER_ON_AFTER_POWER_FAIL + bool + default n + +endif diff --git a/src/mainboard/asrock/h110m/Kconfig.name b/src/mainboard/asrock/h110m/Kconfig.name new file mode 100644 index 0000000..34c1a3c --- /dev/null +++ b/src/mainboard/asrock/h110m/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASROCK_H110M_DVS + bool "H110M-DVS" diff --git a/src/mainboard/asrock/h110m/Makefile.inc b/src/mainboard/asrock/h110m/Makefile.inc new file mode 100644 index 0000000..ce6cf80 --- /dev/null +++ b/src/mainboard/asrock/h110m/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd +bootblock-y += bootblock.c + +ramstage-y += mainboard.c +ramstage-y += ramstage.c +ramstage-y += hda_verb.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/h110m/acpi/dptf.asl b/src/mainboard/asrock/h110m/acpi/dptf.asl new file mode 100644 index 0000000..4453f3b --- /dev/null +++ b/src/mainboard/asrock/h110m/acpi/dptf.asl @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 98 +#define DPTF_CPU_CRITICAL 125 +#define DPTF_CPU_ACTIVE_AC0 91 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 83 +#define DPTF_CPU_ACTIVE_AC3 80 +#define DPTF_CPU_ACTIVE_AC4 75 + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { _SB.PCI0.B0D4, _SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 10000, /* PowerLimitMinimum */ + 31000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 15000, /* PowerLimitMinimum */ + 65000, /* PowerLimitMaximum */ + 28000, /* TimeWindowMinimum */ + 28000, /* TimeWindowMaximum */ + 100 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/skylake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/asrock/h110m/acpi/ec.asl b/src/mainboard/asrock/h110m/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asrock/h110m/acpi/ec.asl diff --git a/src/mainboard/asrock/h110m/acpi/mainboard.asl b/src/mainboard/asrock/h110m/acpi/mainboard.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asrock/h110m/acpi/mainboard.asl diff --git a/src/mainboard/asrock/h110m/acpi/superio.asl b/src/mainboard/asrock/h110m/acpi/superio.asl new file mode 100644 index 0000000..b671e3c --- /dev/null +++ b/src/mainboard/asrock/h110m/acpi/superio.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick tristan@corrick.kiwi + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define NCT6776_SHOW_PP +#define NCT6776_SHOW_SP1 +#define NCT6776_SHOW_KBC +#define NCT6776_SHOW_HWM + +#undef NCT6776_SHOW_GPIO + +#include <superio/nuvoton/nct6776/acpi/superio.asl> diff --git a/src/mainboard/asrock/h110m/acpi_tables.c b/src/mainboard/asrock/h110m/acpi_tables.c new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/asrock/h110m/acpi_tables.c diff --git a/src/mainboard/asrock/h110m/board_info.txt b/src/mainboard/asrock/h110m/board_info.txt new file mode 100644 index 0000000..dfa513e --- /dev/null +++ b/src/mainboard/asrock/h110m/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/Intel/H110M-DVS%20R2.0/ +ROM package: DIP-8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y +Release year: 2015 diff --git a/src/mainboard/asrock/h110m/bootblock.c b/src/mainboard/asrock/h110m/bootblock.c new file mode 100644 index 0000000..96ce205 --- /dev/null +++ b/src/mainboard/asrock/h110m/bootblock.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/gpio.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6791d/nct6791d.h> +#include "include/gpio.h" + +static void early_config_superio(void) +{ + const pnp_devfn_t serial_dev = PNP_DEV(0x2e, NCT6791D_SP1); + nuvoton_enable_serial(serial_dev, CONFIG_TTYS0_BASE); +} + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} + +void bootblock_mainboard_early_init(void) +{ + early_config_superio(); +} diff --git a/src/mainboard/asrock/h110m/cmos.default b/src/mainboard/asrock/h110m/cmos.default new file mode 100644 index 0000000..3296093 --- /dev/null +++ b/src/mainboard/asrock/h110m/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Debug +power_on_after_fail=Disable +nmi=Enable diff --git a/src/mainboard/asrock/h110m/cmos.layout b/src/mainboard/asrock/h110m/cmos.layout new file mode 100644 index 0000000..916db62 --- /dev/null +++ b/src/mainboard/asrock/h110m/cmos.layout @@ -0,0 +1,125 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/asrock/h110m/data.vbt b/src/mainboard/asrock/h110m/data.vbt new file mode 100644 index 0000000..fb03cca --- /dev/null +++ b/src/mainboard/asrock/h110m/data.vbt Binary files differ diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb new file mode 100644 index 0000000..9e2fca0 --- /dev/null +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -0,0 +1,367 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Intel Corporation. +## Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable DPTF + register "dptf_enable" = "1" + + # FSP Configuration + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "HeciEnabled" = "0" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "0" + register "Device4Enable" = "1" + register "SaGv" = "SaGv_Enabled" + register "PmTimerDisabled" = "0" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x10, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0 ,\ + .voltage_limit = 0x0 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x0, \ + .voltage_limit = 0x0 \ + }" + + register "EnableLan" = "0" + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + + register "PmTimerDisabled" = "0" + + # USB + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC4)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[11]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[12]" = "USB2_PORT_MID(OC_SKIP)" + register "usb2_ports[13]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC_SKIP)" + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # SATA + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + + # PCH UART, SPI, I2C + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, \ + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart0] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ + [PchSerialIoIndexUart2] = PchSerialIoDisabled, \ + }" + + # Enable Root port 6(x1) for LAN. + register "PcieRpEnable[5]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[5]" = "1" + # Use SRCCLKREQ1# + register "PcieRpClkReqNumber[5]" = "1" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[5]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[5]" = "1" + # Use CLK SRC 1 + register "PcieRpClkSrcNumber[5]" = "1" + + # Enable Root port 5 (x1) for PCIE slot. + register "PcieRpEnable[4]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[4]" = "1" + # Use SRCCLKREQ2# + register "PcieRpClkReqNumber[4]" = "2" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[4]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[4]" = "1" + # Use CLK SRC 2 + register "PcieRpClkSrcNumber[4]" = "2" + # Use Hot Plug subsystem + register "PcieRpHotPlug[4]" = "1" + + # Enable Root port 7(x1) for PCIE slot. + register "PcieRpEnable[6]" = "1" + # Enable CLKREQ# + register "PcieRpClkReqSupport[6]" = "1" + # Use SRCCLKREQ3# + register "PcieRpClkReqNumber[6]" = "3" + # Enable Advanced Error Reporting + register "PcieRpAdvancedErrorReporting[6]" = "1" + # Enable Latency Tolerance Reporting Mechanism + register "PcieRpLtrEnable[6]" = "1" + # Use CLK SRC 3 + register "PcieRpClkSrcNumber[6]" = "3" + # Use Hot Plug subsystem + register "PcieRpHotPlug[6]" = "1" + + # PL2 override 91W + register "tdp_pl2_override" = "91" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on # Host Bridge + subsystemid 0x1849 0x191f + end + device pci 01.0 on # PEG + subsystemid 0x1849 0x1901 + end + device pci 02.0 on # Integrated Graphics Device + subsystemid 0x1849 0x1912 + end + device pci 14.0 on # USB xHCI + subsystemid 0x1849 0xa131 + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on # Thermal Subsystem + subsystemid 0x1849 0xa131 + end + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1849 0xa131 + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on # SATA + subsystemid 0x1849 0xa102 + end + device pci 19.0 off end # UART #2 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 on end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x1a43 + chip superio/nuvoton/nct6791d + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel + # global + irq 0x1c = 0x10 + irq 0x27 = 0x10 + irq 0x2a = 0x64 + # parallel port + io 0x60 = 0x0378 + irq 0x70 = 7 + drq 0x74 = 4 # No DMA + irq 0xf0 = 0x3c # Printer mode + end + device pnp 2e.2 on # UART A + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # IR + io 0x60 = 0x02f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 KBC + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # Keyboard + irq 0x72 = 12 # Mouse + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6..8 + # WDT1, WDT_MEM, GPIO 0, GPIO 1 + device pnp 2e.8 off end + # GPIO 2, GPIO 3, GPIO 4, GPIO 5 + device pnp 2e.9 off end + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0 + irq 0x70 = 0 + end + device pnp 2e.d off end # BCLK, WDT2, WDT_MEM + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID, Port 80 UART + device pnp 2e.16 off end # Deep sleep + end # superio/nuvoton/nct6791d + chip drivers/pc80/tpm + device pnp 4e.0 on end # TPM module + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/asrock/h110m/dsdt.asl b/src/mainboard/asrock/h110m/dsdt.asl new file mode 100644 index 0000000..f3e216d --- /dev/null +++ b/src/mainboard/asrock/h110m/dsdt.asl @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (_SB) { + Device (PCI0) + { + /* Image processing unit */ + #include <soc/intel/skylake/acpi/ipu.asl> + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + + // Dynamic Platform Thermal Framework + #include "acpi/dptf.asl" + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/asrock/h110m/gma-mainboard.ads b/src/mainboard/asrock/h110m/gma-mainboard.ads new file mode 100644 index 0000000..86a3a62 --- /dev/null +++ b/src/mainboard/asrock/h110m/gma-mainboard.ads @@ -0,0 +1,32 @@ +-- +-- This file is part of the coreboot project. +-- +-- Copyright (C) 2018 Tristan Corrick tristan@corrick.kiwi +-- Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (HDMI1, -- mainboard DVI port + HDMI3, -- mainboard HDMI port + Analog, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/h110m/hda_verb.c b/src/mainboard/asrock/h110m/hda_verb.c new file mode 100644 index 0000000..2fb0fe7 --- /dev/null +++ b/src/mainboard/asrock/h110m/hda_verb.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation + * (Written by Naresh G Solanki naresh.solanki@intel.com for Intel Corp.) + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header ALC887 */ + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x10438445, /* Subsystem ID */ + 15, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0x0, 0x10438445), + AZALIA_PIN_CFG(0x0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x14, 0x01014020), + AZALIA_PIN_CFG(0x0, 0x15, 0x90170110), + AZALIA_PIN_CFG(0x0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0x0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0x0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0x0, 0x1b, 0x02214030), + AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1d, 0x4026c629), + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0), + + /* coreboot specific header */ + 0x80862809, /* Codec Vendor / Device ID: Intel Skylake HDMI */ + 0x80860101, + 0x00000004, + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + AZALIA_SUBVENDOR(0x2, 0x80860101), + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x05, 0x18560010), + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x06, 0x18560020), + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + AZALIA_PIN_CFG(0x2, 0x07, 0x18560030) +}; + +const u32 pc_beep_verbs[] = { +}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/h110m/include/gpio.h b/src/mainboard/asrock/h110m/include/gpio.h new file mode 100644 index 0000000..4ae9911 --- /dev/null +++ b/src/mainboard/asrock/h110m/include/gpio.h @@ -0,0 +1,272 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIO_DVS_H +#define _GPIO_DVS_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +#define H110_PAD_DW0_DW1_CFG(val, config0, config1) \ + _PAD_CFG_STRUCT(val, config0, config1) + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + /* GPIO Group GPP_A */ + H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ + H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ + H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ + H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ + H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ + H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ + H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ + H110_PAD_DW0_DW1_CFG(GPP_A7, 0x84000102, 0x0000001f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ + H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ + H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ + H110_PAD_DW0_DW1_CFG(GPP_A11, 0x84000102, 0x00000023), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A12, 0x84000102, 0x00000024), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), /* SUSWARN# */ + H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ + H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ + H110_PAD_DW0_DW1_CFG(GPP_A16, 0x84000102, 0x00000028), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A17, 0x84000102, 0x00000029), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A18, 0x84000102, 0x0000002a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A19, 0x84000102, 0x0000002b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A20, 0x84000100, 0x0000002c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A21, 0x84000102, 0x0000002d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A22, 0x84000102, 0x0000002e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_A23, 0x84000102, 0x0000002f), /* GPIO */ + /* GPIO Group GPP_B */ + H110_PAD_DW0_DW1_CFG(GPP_B0, 0x84000100, 0x00000030), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B1, 0x84000100, 0x00000031), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B2, 0x84000102, 0x00000032), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B3, 0x44000201, 0x00000033), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B4, 0x84000502, 0x00000034), /* CPU_GP3 */ + H110_PAD_DW0_DW1_CFG(GPP_B5, 0x84000102, 0x00000035), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B6, 0x84000102, 0x00000036), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B7, 0x44000300, 0x00000037), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B8, 0x84000102, 0x00002838), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B9, 0x84000100, 0x00000039), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B10, 0x84000102, 0x0000003a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B11, 0x04000000, 0x0000003b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B12, 0x44000600, 0x0000003c), /* SLP_S0# */ + H110_PAD_DW0_DW1_CFG(GPP_B13, 0x44000600, 0x0000003d), /* PLTRST# */ + H110_PAD_DW0_DW1_CFG(GPP_B14, 0x84000600, 0x0000103e), /* SPKR */ + H110_PAD_DW0_DW1_CFG(GPP_B15, 0x84000102, 0x0000003f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B16, 0x84000102, 0x00000040), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B17, 0x44000201, 0x00000041), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B18, 0x84000100, 0x00000042), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B19, 0x84000102, 0x00000043), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B20, 0x84000102, 0x00000044), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B21, 0x84000102, 0x00000045), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B22, 0x84000100, 0x00000046), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_B23, 0x84000a01, 0x00001047), /* PCHHOT# */ + /* GPIO Group GPP_C */ + H110_PAD_DW0_DW1_CFG(GPP_C0, 0x44000502, 0x00000048), /* SMBCLK */ + H110_PAD_DW0_DW1_CFG(GPP_C1, 0x44000502, 0x00000049), /* SMBDATA */ + H110_PAD_DW0_DW1_CFG(GPP_C2, 0x44000201, 0x0000004a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C3, 0x44000502, 0x0000004b), /* SML0CLK */ + H110_PAD_DW0_DW1_CFG(GPP_C4, 0x44000502, 0x0000004c), /* SML0DATA */ + H110_PAD_DW0_DW1_CFG(GPP_C5, 0x84000100, 0x0000004d), /* GPIO */ + /* GPP_C6 - RESERVED */ + /* GPP_C7 - RESERVED */ + H110_PAD_DW0_DW1_CFG(GPP_C8, 0x84000502, 0x00000050), /* UART0_RXD */ + H110_PAD_DW0_DW1_CFG(GPP_C9, 0x84000600, 0x00000051), /* UART0_TXD */ + H110_PAD_DW0_DW1_CFG(GPP_C10, 0x84000600, 0x00000052), /* UART0_RTS# */ + H110_PAD_DW0_DW1_CFG(GPP_C11, 0x84000502, 0x00000053), /* UART0_CTS# */ + H110_PAD_DW0_DW1_CFG(GPP_C12, 0x84000102, 0x00000054), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C13, 0x84000102, 0x00000055), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C14, 0x84000102, 0x00000056), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C15, 0x84000102, 0x00000057), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C16, 0x84000102, 0x00000058), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C17, 0x84000102, 0x00000059), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C18, 0x84000102, 0x0000005a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C19, 0x84000102, 0x0000005b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_C20, 0x84000502, 0x0000005c), /* UART2_RXD */ + H110_PAD_DW0_DW1_CFG(GPP_C21, 0x84000600, 0x0000005d), /* UART2_TXD */ + H110_PAD_DW0_DW1_CFG(GPP_C22, 0x84000600, 0x0000005e), /* UART2_RTS# */ + H110_PAD_DW0_DW1_CFG(GPP_C23, 0x40880102, 0x0000005f), /* GPIO */ + /* GPIO Group GPP_D */ + H110_PAD_DW0_DW1_CFG(GPP_D0, 0x84000102, 0x00000060), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D1, 0x84000102, 0x00000061), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D2, 0x84000102, 0x00000062), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D3, 0x84000102, 0x00000063), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D4, 0x84000102, 0x00000064), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D5, 0x84000402, 0x00000065), /* I2S_SFRM */ + H110_PAD_DW0_DW1_CFG(GPP_D6, 0x84000600, 0x00000066), /* I2S_TXD */ + H110_PAD_DW0_DW1_CFG(GPP_D7, 0x84000502, 0x00000067), /* I2S_RXD */ + H110_PAD_DW0_DW1_CFG(GPP_D8, 0x84000402, 0x00000068), /* I2S_SCLK */ + H110_PAD_DW0_DW1_CFG(GPP_D9, 0x84000102, 0x00000069), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D10, 0x84000102, 0x0000006a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D11, 0x84000102, 0x0000006b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D12, 0x84000102, 0x0000006c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D13, 0x84000102, 0x0000006d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D14, 0x84000100, 0x0000006e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D15, 0x84000100, 0x0000006f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D16, 0x84000102, 0x00000070), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D17, 0x84000102, 0x00000071), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D18, 0x84000102, 0x00000072), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D19, 0x84000500, 0x00003073), /* DMIC_CLK0 */ + H110_PAD_DW0_DW1_CFG(GPP_D20, 0x84000500, 0x00003074), /* DMIC_DATA0 */ + H110_PAD_DW0_DW1_CFG(GPP_D21, 0x84000102, 0x00000075), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D22, 0x84000102, 0x00000076), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_D23, 0x84000102, 0x00000077), /* GPIO */ + /* GPIO Group GPP_E */ + H110_PAD_DW0_DW1_CFG(GPP_E0, 0x84000502, 0x00003018), /* SATAXPCIE0 */ + H110_PAD_DW0_DW1_CFG(GPP_E1, 0x84000502, 0x00003019), /* SATAXPCIE1 */ + H110_PAD_DW0_DW1_CFG(GPP_E2, 0x84000502, 0x0000301a), /* SATAXPCIE2 */ + H110_PAD_DW0_DW1_CFG(GPP_E3, 0x84000500, 0x0000001b), /* CPU_GP0 */ + /* SATA_DEVSLP0 */ + H110_PAD_DW0_DW1_CFG(GPP_E4, 0x84000500, 0x0000001c), + /* SATA_DEVSLP1 */ + H110_PAD_DW0_DW1_CFG(GPP_E5, 0x84000500, 0x0000001d), + /* SATA_DEVSLP2 */ + H110_PAD_DW0_DW1_CFG(GPP_E6, 0x84000500, 0x0000001e), + H110_PAD_DW0_DW1_CFG(GPP_E7, 0x84000102, 0x0000001f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_E8, 0x84000600, 0x00000020), /* SATA_LED# */ + H110_PAD_DW0_DW1_CFG(GPP_E9, 0x44000502, 0x00000021), /* USB_OC0# */ + H110_PAD_DW0_DW1_CFG(GPP_E10, 0x44000502, 0x00000022), /* USB_OC1# */ + H110_PAD_DW0_DW1_CFG(GPP_E11, 0x44000502, 0x00000023), /* USB_OC2# */ + H110_PAD_DW0_DW1_CFG(GPP_E12, 0x44000502, 0x00000024), /* USB_OC3# */ + /* GPIO Group GPP_F */ + H110_PAD_DW0_DW1_CFG(GPP_F0, 0x84000102, 0x00000025), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F1, 0x84000502, 0x00003026), /* SATAXPCIE4 */ + H110_PAD_DW0_DW1_CFG(GPP_F2, 0x44000300, 0x00000027), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F3, 0x84000102, 0x00000028), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F4, 0x84000102, 0x00000029), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F5, 0x84000102, 0x0000002a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F6, 0x84000102, 0x0000002b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F7, 0x84000102, 0x0000002c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F8, 0x84000102, 0x0000002d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F9, 0x84000102, 0x0000002e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F10, 0x80100102, 0x0000002f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F11, 0x84000102, 0x00000030), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F12, 0x80900102, 0x00000031), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F13, 0x80100102, 0x00000032), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F14, 0x40900102, 0x00000033), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F15, 0x44000502, 0x00000034), /* USB_OC4# */ + H110_PAD_DW0_DW1_CFG(GPP_F16, 0x44000502, 0x00000035), /* USB_OC5# */ + H110_PAD_DW0_DW1_CFG(GPP_F17, 0x44000502, 0x00000036), /* USB_OC6# */ + H110_PAD_DW0_DW1_CFG(GPP_F18, 0x84000201, 0x00000037), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F19, 0x84000100, 0x00000038), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F20, 0x84000102, 0x00000039), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F21, 0x84000102, 0x0000003a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F22, 0x84000102, 0x0000003b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_F23, 0x84000102, 0x0000003c), /* GPIO */ + /* GPIO Group GPP_G */ + H110_PAD_DW0_DW1_CFG(GPP_G0, 0xc4000102, 0x0000003d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G1, 0xc4000102, 0x0000003e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G2, 0xc4000100, 0x0000003f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G3, 0xc4000100, 0x00000040), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G4, 0x44000200, 0x00000041), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G5, 0xc4000102, 0x00000042), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G6, 0xc0800102, 0x00000043), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G7, 0xc4000102, 0x00000044), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G8, 0x84000100, 0x00000045), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G9, 0x84000100, 0x00000046), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G10, 0x84000102, 0x00000047), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G11, 0x84000100, 0x00000048), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G12, 0x80800102, 0x00000049), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G13, 0x84000201, 0x0000004a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G14, 0x80800102, 0x0000004b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G15, 0x84000200, 0x0000004c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G16, 0x84000201, 0x0000104d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G17, 0x84000102, 0x0000004e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G18, 0x80100102, 0x0000004f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G19, 0x84000500, 0x00000050), /* SMI# */ + H110_PAD_DW0_DW1_CFG(GPP_G20, 0x84000102, 0x00000051), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G21, 0x84000102, 0x00000052), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G22, 0x84000102, 0x00000053), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_G23, 0x84000102, 0x00000054), /* GPIO */ + /* GPIO Group GPP_H */ + H110_PAD_DW0_DW1_CFG(GPP_H0, 0x84000102, 0x00000055), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H1, 0x44000300, 0x00000056), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H2, 0x84000102, 0x00000057), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H3, 0x84000102, 0x00000058), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H4, 0x84000102, 0x00000059), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H5, 0x84000102, 0x0000005a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H6, 0x84000102, 0x0000005b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H7, 0x84000102, 0x0000005c), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H8, 0x84000100, 0x0000005d), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H9, 0x84000102, 0x0000005e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H10, 0x84000102, 0x0000005f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H11, 0x84000102, 0x00000060), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H12, 0x84000100, 0x00000061), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H13, 0x80100102, 0x00000062), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H14, 0x80100102, 0x00000063), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H15, 0x80100100, 0x00000064), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H16, 0x80000102, 0x00000065), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H17, 0x84000201, 0x00000066), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H18, 0x84000102, 0x00000067), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H19, 0x84000102, 0x00000068), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H20, 0x84000102, 0x00000069), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H21, 0x84000102, 0x0000006a), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H22, 0x84000102, 0x0000006b), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPP_H23, 0x04000100, 0x0000006c), /* GPIO */ + /* GPIO Group GPD */ + H110_PAD_DW0_DW1_CFG(GPD0, 0x84000102, 0x00000018), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD1, 0x04000200, 0x00000019), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD2, 0x00000602, 0x00003c1a), /* LAN_WAKE# */ + H110_PAD_DW0_DW1_CFG(GPD3, 0x04000502, 0x0000301b), /* PWRBTN# */ + H110_PAD_DW0_DW1_CFG(GPD4, 0x04000600, 0x0000001c), /* SLP_S3# */ + H110_PAD_DW0_DW1_CFG(GPD5, 0x04000600, 0x0000001d), /* SLP_S4# */ + H110_PAD_DW0_DW1_CFG(GPD6, 0x84000102, 0x0000001e), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD7, 0x84000103, 0x0000001f), /* GPIO */ + H110_PAD_DW0_DW1_CFG(GPD8, 0x04000600, 0x00000020), /* SUSCLK */ + H110_PAD_DW0_DW1_CFG(GPD9, 0x04000600, 0x00000021), /* SLP_WLAN# */ + H110_PAD_DW0_DW1_CFG(GPD10, 0x04000600, 0x00000022), /* SLP_S5# */ + H110_PAD_DW0_DW1_CFG(GPD11, 0x04000200, 0x00000023), /* GPIO */ + /* GPIO Group GPP_I */ + H110_PAD_DW0_DW1_CFG(GPP_I0, 0x84000502, 0x0000006d), /* DDPB_HPD0 */ + H110_PAD_DW0_DW1_CFG(GPP_I1, 0x84000502, 0x0000006e), /* DDPC_HPD1 */ + H110_PAD_DW0_DW1_CFG(GPP_I2, 0x84000500, 0x0000006f), /* DDPD_HPD2 */ + H110_PAD_DW0_DW1_CFG(GPP_I3, 0x84000502, 0x00000070), /* DDPE_HPD3 */ + H110_PAD_DW0_DW1_CFG(GPP_I4, 0x84000100, 0x00000071), /* GPIO */ + /* DDPB_CTRLCLK */ + H110_PAD_DW0_DW1_CFG(GPP_I5, 0x84000500, 0x00000072), + /* DDPB_CTRLDATA */ + H110_PAD_DW0_DW1_CFG(GPP_I6, 0x84000500, 0x00001073), + /* DDPC_CTRLCLK */ + H110_PAD_DW0_DW1_CFG(GPP_I7, 0x84000500, 0x00000074), + /* DDPC_CTRLDATA */ + H110_PAD_DW0_DW1_CFG(GPP_I8, 0x84000500, 0x00001075), + /* DDPD_CTRLCLK */ + H110_PAD_DW0_DW1_CFG(GPP_I9, 0x84000500, 0x00000076), + /* DDPD_CTRLDATA */ + H110_PAD_DW0_DW1_CFG(GPP_I10, 0x84000500, 0x00001077), +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + /* GPIO Group GPP_A */ + H110_PAD_DW0_DW1_CFG(GPP_A0, 0x84000502, 0x00000018), /* RCIN# */ + H110_PAD_DW0_DW1_CFG(GPP_A1, 0x84000402, 0x00003019), /* LAD0 */ + H110_PAD_DW0_DW1_CFG(GPP_A2, 0x84000402, 0x0000301a), /* LAD1 */ + H110_PAD_DW0_DW1_CFG(GPP_A3, 0x84000402, 0x0000301b), /* LAD2 */ + H110_PAD_DW0_DW1_CFG(GPP_A4, 0x84000402, 0x0000301c), /* LAD3 */ + H110_PAD_DW0_DW1_CFG(GPP_A5, 0x84000600, 0x0000001d), /* LFRAME# */ + H110_PAD_DW0_DW1_CFG(GPP_A6, 0x84000402, 0x0000001e), /* SERIRQ */ + H110_PAD_DW0_DW1_CFG(GPP_A8, 0x84000500, 0x00000020), /* CLKRUN# */ + H110_PAD_DW0_DW1_CFG(GPP_A9, 0x84000600, 0x00001021), /* CLKOUT_LPC0 */ + H110_PAD_DW0_DW1_CFG(GPP_A10, 0x84000600, 0x00001022), /* CLKOUT_LPC1 */ + /* ---- */ + /* SUSWARN#/SUSPWRDNACK */ + H110_PAD_DW0_DW1_CFG(GPP_A13, 0x44000600, 0x00000025), + H110_PAD_DW0_DW1_CFG(GPP_A14, 0x44000600, 0x00000026), /* SUS_STAT# */ + H110_PAD_DW0_DW1_CFG(GPP_A15, 0x44000502, 0x00003027), /* SUS_ACK# */ +}; + +#endif diff --git a/src/mainboard/asrock/h110m/mainboard.c b/src/mainboard/asrock/h110m/mainboard.c new file mode 100644 index 0000000..4c1c6cd --- /dev/null +++ b/src/mainboard/asrock/h110m/mainboard.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Tristan Corrick tristan@corrick.kiwi + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> + +static void mainboard_enable(struct device *dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asrock/h110m/ramstage.c b/src/mainboard/asrock/h110m/ramstage.c new file mode 100644 index 0000000..c93e84c --- /dev/null +++ b/src/mainboard/asrock/h110m/ramstage.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include "include/gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + params->CdClock = 3; + /* Enable Virtual Channel 1 */ + params->PchHdaVcType = 0x1; +} diff --git a/src/mainboard/asrock/h110m/romstage.c b/src/mainboard/asrock/h110m/romstage.c new file mode 100644 index 0000000..4961a79 --- /dev/null +++ b/src/mainboard/asrock/h110m/romstage.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2019 Maxim Polyakov max.senia.poliak@gmail.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <string.h> +#include <spd_bin.h> + +#define RCOMP_TARGET_PARAMS 0x5 + +static void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +static void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 200, 81, 162 }; + memcpy(rcomp_ptr, RcompResistor, + sizeof(RcompResistor)); +} + +static void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { + 100, 40, 40, 23, 40 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = { 0x50, 0x51, 0x52, 0x53, }, + }; + + mem_cfg = &mupd->FspmConfig; + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; + mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; + mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + dump_spd_info(&blk); + + /* use virtual channel 1 for the dmi interface of the PCH */ + mupd->FspmTestConfig.DmiVc1 = 1; + + /* desktop type */ + mem_cfg->UserBd = BOARD_TYPE_DESKTOP; +}
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