[M] Change in coreboot[master]: cpu/x86/smm: Add PCI BAR store functionality

[Nico Huber (Code Review)]

Attention is currently required from: Arthur Heymans, Robert Zieba, Martin Roth, Karthik Ramasubramanian, Felix Held.

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67931 )

Change subject: cpu/x86/smm: Add PCI BAR store functionality
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Patch Set 5:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/67931/comment/74e6febd_98d341f3 
PS2, Line 9: n certain cases data within protected memmory areas like SMRAM could
           : be leaked or modified if an attacker remaps PCI BARs to point within
           : that area.
> I thought the hardware makes sure that you cannot put BARs where memory resides.

You can, but the device will most likely not work.

One attack vector is not so much about what the hardware does with a
wrong BAR setting, but what the software (SMI handler) does. Imagine
the BAR (register) as a scratch pad, it doesn't matter if the device
can work with the value in there. Then, if the SMI handler would read
that register (as an address) to access the device, it might acciden-
tally access protected memory instead.

Another way to see it: the register can be used to pass a pointer into
the SMI handler. It shouldn't trust that pointer.