Change in coreboot[master]: mb/purism/librem_whl: Convert GPIOs to macros - coreboot-gerrit

15 Aug 2020

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44503 )
Change subject: mb/purism/librem_whl: Convert GPIOs to macros
......................................................................
mb/purism/librem_whl: Convert GPIOs to macros
Convert raw GPIOs to coreboot macros using newly-added support
for Cannon/Whiskey/Coffee/Cometlake SoCs to intelp2m
Test: build/boot Librem Mini, no smoke released.
Change-Id: I6ac747ad4e650c24d2b7e34228ff74140c51a0c1
Signed-off-by: Matt DeVillier matt.devillier@puri.sm
---
M src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c
1 file changed, 751 insertions(+), 189 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/44503/1

diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c
index 492d978..254510e 100644
--- a/src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c
+++ b/src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c
@@ -2,224 +2,786 @@
#include <variant/gpio.h>
-/* Pad configuration in ramstage. */
+/* Pad configuration was generated automatically using intelp2m utility */
 static const struct pad_config gpio_table[] = {
+	/* ------- GPIO Community 0 ------- */
+
    /* ------- GPIO Group GPP_A ------- */
-	_PAD_CFG_STRUCT(GPP_A0,  0x44000702, 0x0000),	/* RCIN#               */
-	_PAD_CFG_STRUCT(GPP_A1,  0x44000702, 0x3c00),	/* LAD0                */
-	_PAD_CFG_STRUCT(GPP_A2,  0x44000702, 0x3c00),	/* LAD1                */
-	_PAD_CFG_STRUCT(GPP_A3,  0x44000702, 0x3c00),	/* LAD2                */
-	_PAD_CFG_STRUCT(GPP_A4,  0x44000702, 0x3c00),	/* LAD3                */
-	_PAD_CFG_STRUCT(GPP_A5,  0x44000700, 0x0000),	/* LFRAME#             */
-	_PAD_CFG_STRUCT(GPP_A6,  0x44000700, 0x0000),	/* SERIRQ              */
-	_PAD_CFG_STRUCT(GPP_A7,  0x84000200, 0x0000),	/* PIRQA#              */
-	_PAD_CFG_STRUCT(GPP_A8,  0x44000700, 0x0000),	/* CLKRUN#             */
-	_PAD_CFG_STRUCT(GPP_A9,  0x44000700, 0x1000),	/* CLKOUT_LPC0         */
-	_PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000),	/* CLKOUT_LPC1         */
-	_PAD_CFG_STRUCT(GPP_A11, 0x40880201, 0x0000),	/* PME#                */
-	_PAD_CFG_STRUCT(GPP_A12, 0x84000201, 0x0000),	/* BM_BUSY#            */
-	_PAD_CFG_STRUCT(GPP_A13, 0x84000201, 0x0000),	/* SUSWARN#/SUSPWRDNACK*/
-	_PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0000),	/* SUS_STAT#           */
-	_PAD_CFG_STRUCT(GPP_A15, 0x84000201, 0x0000),	/* SUSACK#             */
-	_PAD_CFG_STRUCT(GPP_A16, 0x84000200, 0x3000),	/* SD_1P8_SEL          */
-	_PAD_CFG_STRUCT(GPP_A17, 0x84000201, 0x0000),	/* SD_VDD1_PWR_EN#     */
-	_PAD_CFG_STRUCT(GPP_A18, 0x44000300, 0x3000),	/* ISH_GP0             */
-	_PAD_CFG_STRUCT(GPP_A19, 0x44000300, 0x3000),	/* ISH_GP1             */
-	_PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x3000),	/* ISH_GP2             */
-	_PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x3000),	/* ISH_GP3             */
-	_PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x3000),	/* ISH_GP4             */
-	_PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x3000),	/* ISH_GP5             */
+	/* GPP_A0 - RCIN# */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+
+	/* GPP_A1 - LAD0 */
+	/* DW0: 0x44000702, DW1: 0x00003c00 */
+	PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1),
+
+	/* GPP_A2 - LAD1 */
+	/* DW0: 0x44000702, DW1: 0x00003c00 */
+	PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1),
+
+	/* GPP_A3 - LAD2 */
+	/* DW0: 0x44000702, DW1: 0x00003c00 */
+	PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1),
+
+	/* GPP_A4 - LAD3 */
+	/* DW0: 0x44000702, DW1: 0x00003c00 */
+	PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1),
+
+	/* GPP_A5 - LFRAME# */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+
+	/* GPP_A6 - SERIRQ */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+
+	/* GPP_A7 - GPIO */
+	/* DW0: 0x44000200, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_A7, 0, DEEP),
+
+	/* GPP_A8 - CLKRUN# */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+
+	/* GPP_A9 - CLKOUT_LPC0 */
+	/* DW0: 0x44000700, DW1: 0x00001000 */
+	PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1),
+
+	/* GPP_A10 - CLKOUT_LPC1 */
+	/* DW0: 0x44000700, DW1: 0x00001000 */
+	PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1),
+
+	/* GPP_A11 - GPIO */
+	/* DW0: 0x80880201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_A11, 1, PLTRST),
+
+	/* GPP_A12 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_A12, 1, PLTRST),
+
+	/* GPP_A13 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_A13, 1, PLTRST),
+
+	/* GPP_A14 - SUS_STAT# */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+
+	/* GPP_A15 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_A15, 1, PLTRST),
+
+	/* GPP_A16 - GPIO */
+	/* DW0: 0x84000200, DW1: 0x00003000 */
+	PAD_CFG_TERM_GPO(GPP_A16, 0, UP_20K, PLTRST),
+
+	/* GPP_A17 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_A17, 1, PLTRST),
+
+	/* GPP_A18 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00003000 */
+	PAD_NC(GPP_A18, UP_20K),
+
+	/* GPP_A19 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00003000 */
+	PAD_NC(GPP_A19, UP_20K),
+
+	/* GPP_A20 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00003000 */
+	PAD_NC(GPP_A20, UP_20K),
+
+	/* GPP_A21 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00003000 */
+	PAD_NC(GPP_A21, UP_20K),
+
+	/* GPP_A22 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00003000 */
+	PAD_NC(GPP_A22, UP_20K),
+
+	/* GPP_A23 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00003000 */
+	PAD_NC(GPP_A23, UP_20K),
/* ------- GPIO Group GPP_B ------- */
-	_PAD_CFG_STRUCT(GPP_B0,  0x84000700, 0x0000),	/* Reserved            */
-	_PAD_CFG_STRUCT(GPP_B1,  0x84000700, 0x0000),	/* Reserved            */
-	_PAD_CFG_STRUCT(GPP_B2,  0x84000201, 0x0000),	/* VRALERT#            */
-	_PAD_CFG_STRUCT(GPP_B3,  0x84000201, 0x0000),	/* CPU_GP2             */
-	_PAD_CFG_STRUCT(GPP_B4,  0x84000201, 0x0000),	/* CPU_GP3             */
-	_PAD_CFG_STRUCT(GPP_B5,  0x44000300, 0x0000),	/* SRCCLKREQ0#         */
-	_PAD_CFG_STRUCT(GPP_B6,  0x44000300, 0x0000),	/* SRCCLKREQ1#         */
-	_PAD_CFG_STRUCT(GPP_B7,  0x44000300, 0x0000),	/* SRCCLKREQ2#         */
-	_PAD_CFG_STRUCT(GPP_B8,  0x44000300, 0x0000),	/* SRCCLKREQ3#         */
-	_PAD_CFG_STRUCT(GPP_B9,  0x44000300, 0x0000),	/* SRCCLKREQ4#         */
-	_PAD_CFG_STRUCT(GPP_B10, 0x44000300, 0x0000),	/* SRCCLKREQ5#         */
-	_PAD_CFG_STRUCT(GPP_B11, 0x84000201, 0x0000),	/* EXT_PWR_GATE#       */
-	_PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0000),	/* SLP_S0#             */
-	_PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0000),	/* PLTRST#             */
-	_PAD_CFG_STRUCT(GPP_B14, 0x84000201, 0x0000),	/* SPKR                */
-	_PAD_CFG_STRUCT(GPP_B15, 0x80000701, 0x0000),	/* GSPI0_CS0#          */
-	_PAD_CFG_STRUCT(GPP_B16, 0x84000601, 0x0000),	/* GSPI0_CLK           */
-	_PAD_CFG_STRUCT(GPP_B17, 0x44000502, 0x0000),	/* GSPI0_MISO          */
-	_PAD_CFG_STRUCT(GPP_B18, 0x84000601, 0x0000),	/* GSPI0_MOSI          */
-	_PAD_CFG_STRUCT(GPP_B19, 0x84000400, 0x0000),	/* GSPI1_CS0#          */
-	_PAD_CFG_STRUCT(GPP_B20, 0x84000400, 0x0000),	/* GSPI1_CLK           */
-	_PAD_CFG_STRUCT(GPP_B21, 0x84000402, 0x0000),	/* GSPI1_MISO          */
-	_PAD_CFG_STRUCT(GPP_B22, 0x84000400, 0x0000),	/* GSPI1_MOSI          */
-	_PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x0000),	/* SML1ALERT#          */
+	/* GPP_B0 - Reserved */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+
+	/* GPP_B1 - Reserved */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+
+	/* GPP_B2 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_B2, 1, PLTRST),
+
+	/* GPP_B3 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_B3, 1, PLTRST),
+
+	/* GPP_B4 - GPIO */
+	/* DW0: 0x44000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+
+	/* GPP_B5 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_B5, NONE),
+
+	/* GPP_B6 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_B6, NONE),
+
+	/* GPP_B7 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_B7, NONE),
+
+	/* GPP_B8 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_B8, NONE),
+
+	/* GPP_B9 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_B9, NONE),
+
+	/* GPP_B10 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_B10, NONE),
+
+	/* GPP_B11 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_B11, 1, PLTRST),
+
+	/* GPP_B12 - SLP_S0# */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+
+	/* GPP_B13 - PLTRST# */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+
+	/* GPP_B14 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_B14, 1, PLTRST),
+
+	/* GPP_B15 - GSPI0_CS0# */
+	/* DW0: 0x00000701, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B15, NONE, PWROK, NF1),
+
+	/* GPP_B16 - GSPI0_CLK */
+	/* DW0: 0x84000601, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B16, NONE, PLTRST, NF1),
+
+	/* GPP_B17 - GSPI0_MISO */
+	/* DW0: 0x44000502, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+
+	/* GPP_B18 - GSPI0_MOSI */
+	/* DW0: 0x84000601, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B18, NONE, PLTRST, NF1),
+
+	/* GPP_B19 - GSPI1_CS0# */
+	/* DW0: 0x84000400, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B19, NONE, PLTRST, NF1),
+
+	/* GPP_B20 - GSPI1_CLK */
+	/* DW0: 0x84000400, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B20, NONE, PLTRST, NF1),
+
+	/* GPP_B21 - GSPI1_MISO */
+	/* DW0: 0x84000402, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B21, NONE, PLTRST, NF1),
+
+	/* GPP_B22 - GSPI1_MOSI */
+	/* DW0: 0x84000400, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_B22, NONE, PLTRST, NF1),
+
+	/* GPP_B23 - GPIO */
+	/* DW0: 0x44000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_B23, 1, DEEP),
/* ------- GPIO Group GPP_G ------- */
-	_PAD_CFG_STRUCT(GPP_G0,  0x84000200, 0x0000),	/* SD_CMD              */
-	_PAD_CFG_STRUCT(GPP_G1,  0x84000300, 0x0000),	/* SD_DATA0            */
-	_PAD_CFG_STRUCT(GPP_G2,  0x84000300, 0x0000),	/* SD_DATA1            */
-	_PAD_CFG_STRUCT(GPP_G3,  0x84000300, 0x0000),	/* SD_DATA2            */
-	_PAD_CFG_STRUCT(GPP_G4,  0x84000300, 0x0000),	/* SD_DATA3            */
-	_PAD_CFG_STRUCT(GPP_G5,  0x84000300, 0x3000),	/* SD3_CD#             */
-	_PAD_CFG_STRUCT(GPP_G6,  0x84000300, 0x0000),	/* SD3_CLK             */
-	_PAD_CFG_STRUCT(GPP_G7,  0x84000300, 0x1000),	/* SD3_WP              */
+	/* GPP_G0 - GPIO */
+	/* DW0: 0x04000200, DW1: 0x00001000 */
+	PAD_CFG_TERM_GPO(GPP_G0, 0, DN_20K, PWROK),
+
+	/* GPP_G1 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_G1, NONE),
+
+	/* GPP_G2 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_G2, NONE),
+
+	/* GPP_G3 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_G3, NONE),
+
+	/* GPP_G4 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_G4, NONE),
+
+	/* GPP_G5 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00003000 */
+	PAD_NC(GPP_G5, UP_20K),
+
+	/* GPP_G6 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_G6, NONE),
+
+	/* GPP_G7 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00001000 */
+	PAD_NC(GPP_G7, DN_20K),
+
+	/* ------- GPIO Community 1 ------- */
/* ------- GPIO Group GPP_D ------- */
-	_PAD_CFG_STRUCT(GPP_D0,  0x44000300, 0x0000),	/* SPI1_CS#            */
-	_PAD_CFG_STRUCT(GPP_D1,  0x44000300, 0x0000),	/* SPI1_CLK            */
-	_PAD_CFG_STRUCT(GPP_D2,  0x44000300, 0x0000),	/* SPI1_MISO           */
-	_PAD_CFG_STRUCT(GPP_D3,  0x44000300, 0x0000),	/* SPI1_MOSI           */
-	_PAD_CFG_STRUCT(GPP_D4,  0x44000300, 0x0000),	/* IMGCLKOUT0          */
-	_PAD_CFG_STRUCT(GPP_D5,  0x44000700, 0x0000),	/* ISH_I2C0_SDA        */
-	_PAD_CFG_STRUCT(GPP_D6,  0x44000700, 0x0000),	/* ISH_I2C0_SCL        */
-	_PAD_CFG_STRUCT(GPP_D7,  0x84000201, 0x0000),	/* ISH_I2C1_SDA        */
-	_PAD_CFG_STRUCT(GPP_D8,  0x84000200, 0x0000),	/* ISH_I2C1_SCL        */
-	_PAD_CFG_STRUCT(GPP_D9,  0x84000201, 0x0000),	/* ISH_SPI_CS#         */
-	_PAD_CFG_STRUCT(GPP_D10, 0x84000201, 0x0000),	/* ISH_SPI_CLK         */
-	_PAD_CFG_STRUCT(GPP_D11, 0x44000201, 0x3000),	/* ISH_SPI_MISO        */
-	_PAD_CFG_STRUCT(GPP_D12, 0x42100102, 0x3000),	/* ISH_SPI_MOSI        */
-	_PAD_CFG_STRUCT(GPP_D13, 0x44000201, 0x0000),	/* ISH_UART0_RXD       */
-	_PAD_CFG_STRUCT(GPP_D14, 0x84000201, 0x0000),	/* ISH_UART0_TXD       */
-	_PAD_CFG_STRUCT(GPP_D15, 0x84000201, 0x0000),	/* ISH_UART0_RTS#      */
-	_PAD_CFG_STRUCT(GPP_D16, 0x44000200, 0x0000),	/* ISH_UART0_CTS#      */
-	_PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0000),	/* DMIC_CLK1           */
-	_PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x0000),	/* DMIC_DATA1          */
-	_PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0000),	/* DMIC_CLK0           */
-	_PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0000),	/* DMIC_DATA0          */
-	_PAD_CFG_STRUCT(GPP_D21, 0x44000300, 0x0000),	/* SPI1_IO2            */
-	_PAD_CFG_STRUCT(GPP_D22, 0x44000300, 0x0000),	/* SPI1_IO3            */
-	_PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x0000),	/* I2S_MCLK            */
+	/* GPP_D0 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_D0, NONE),
+
+	/* GPP_D1 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_D1, NONE),
+
+	/* GPP_D2 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_D2, NONE),
+
+	/* GPP_D3 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_D3, NONE),
+
+	/* GPP_D4 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_D4, NONE),
+
+	/* GPP_D5 - ISH_I2C0_SDA */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+
+	/* GPP_D6 - ISH_I2C0_SCL */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+
+	/* GPP_D7 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_D7, 1, PLTRST),
+
+	/* GPP_D8 - GPIO */
+	/* DW0: 0x84000200, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_D8, 0, PLTRST),
+
+	/* GPP_D9 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_D9, 1, PLTRST),
+
+	/* GPP_D10 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_D10, 1, PLTRST),
+
+	/* GPP_D11 - GPIO */
+	/* DW0: 0x44000201, DW1: 0x00003000 */
+	PAD_CFG_TERM_GPO(GPP_D11, 1, UP_20K, DEEP),
+
+	/* GPP_D12 - GPIO */
+	/* DW0: 0x42100102, DW1: 0x00003000 */
+	PAD_CFG_GPI_APIC(GPP_D12, UP_20K, DEEP, EDGE_SINGLE, NONE),
+
+	/* GPP_D13 - GPIO */
+	/* DW0: 0x04000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_D13, 1, RSMRST),
+
+	/* GPP_D14 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_D14, 1, PLTRST),
+
+	/* GPP_D15 - GPIO */
+	/* DW0: 0x44000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_D15, 1, DEEP),
+
+	/* GPP_D16 - GPIO */
+	/* DW0: 0x04000200, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_D16, 0, RSMRST),
+
+	/* GPP_D17 - DMIC_CLK1 */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+
+	/* GPP_D18 - DMIC_DATA1 */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+
+	/* GPP_D19 - DMIC_CLK0 */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+
+	/* GPP_D20 - DMIC_DATA0 */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+
+	/* GPP_D21 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_D21, NONE),
+
+	/* GPP_D22 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_D22, NONE),
+
+	/* GPP_D23 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_D23, NONE),
/* ------- GPIO Group GPP_F ------- */
-	_PAD_CFG_STRUCT(GPP_F0,  0x84000301, 0x0000),	/* CNV_PA_BLANKING     */
-	_PAD_CFG_STRUCT(GPP_F1,  0x84000200, 0x0000),	/* GPIO                */
-	_PAD_CFG_STRUCT(GPP_F2,  0x84000201, 0x3000),	/* GPIO                */
-	_PAD_CFG_STRUCT(GPP_F3,  0x84000200, 0x3000),	/* GPIO                */
-	_PAD_CFG_STRUCT(GPP_F4,  0x44000700, 0x3000),	/* CNV_BRI_DT          */
-	_PAD_CFG_STRUCT(GPP_F5,  0x44000702, 0x3000),	/* CNV_BRI_RSP         */
-	_PAD_CFG_STRUCT(GPP_F6,  0x44000700, 0x3000),	/* CNV_RGI_DT          */
-	_PAD_CFG_STRUCT(GPP_F7,  0x44000702, 0x3000),	/* CNV_RGI_RSP         */
-	_PAD_CFG_STRUCT(GPP_F8,  0x44000300, 0x0000),	/* CNV_MFUART2_RXD     */
-	_PAD_CFG_STRUCT(GPP_F9,  0x44000300, 0x0000),	/* CNV_MFUART2_TXD     */
-	_PAD_CFG_STRUCT(GPP_F10, 0x84000201, 0x0000),	/* GPIO                */
-	_PAD_CFG_STRUCT(GPP_F11, 0x44000300, 0x0000),	/* EMMC_CMD            */
-	_PAD_CFG_STRUCT(GPP_F12, 0x44000300, 0x0000),	/* EMMC_DATA0          */
-	_PAD_CFG_STRUCT(GPP_F13, 0x44000300, 0x0000),	/* EMMC_DATA1          */
-	_PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x0000),	/* EMMC_DATA2          */
-	_PAD_CFG_STRUCT(GPP_F15, 0x44000300, 0x0000),	/* EMMC_DATA3          */
-	_PAD_CFG_STRUCT(GPP_F16, 0x44000300, 0x0000),	/* EMMC_DATA4          */
-	_PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x0000),	/* EMMC_DATA5          */
-	_PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x0000),	/* EMMC_DATA6          */
-	_PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x0000),	/* EMMC_DATA7          */
-	_PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x0000),	/* EMMC_RCLK           */
-	_PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x0000),	/* EMMC_CLK            */
-	_PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x0000),	/* EMMC_RESET#         */
-	_PAD_CFG_STRUCT(GPP_F23, 0x44000700, 0x1000),	/* A4WP_PRESENT        */
+	/* GPP_F0 - GPIO */
+	/* DW0: 0x00000301, DW1: 0x00000000 */
+	PAD_NC(GPP_F0, NONE),
+
+	/* GPP_F1 - GPIO */
+	/* DW0: 0x04000200, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_F1, 0, RSMRST),
+
+	/* GPP_F2 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00003000 */
+	PAD_CFG_TERM_GPO(GPP_F2, 1, UP_20K, PLTRST),
+
+	/* GPP_F3 - GPIO */
+	/* DW0: 0x84000200, DW1: 0x00003000 */
+	PAD_CFG_TERM_GPO(GPP_F3, 0, UP_20K, PLTRST),
+
+	/* GPP_F4 - CNV_BRI_DT */
+	/* DW0: 0x44000700, DW1: 0x00003000 */
+	PAD_CFG_NF(GPP_F4, UP_20K, DEEP, NF1),
+
+	/* GPP_F5 - CNV_BRI_RSP */
+	/* DW0: 0x44000702, DW1: 0x00003000 */
+	PAD_CFG_NF(GPP_F5, UP_20K, DEEP, NF1),
+
+	/* GPP_F6 - CNV_RGI_DT */
+	/* DW0: 0x44000700, DW1: 0x00003000 */
+	PAD_CFG_NF(GPP_F6, UP_20K, DEEP, NF1),
+
+	/* GPP_F7 - CNV_RGI_RSP */
+	/* DW0: 0x44000702, DW1: 0x00003000 */
+	PAD_CFG_NF(GPP_F7, UP_20K, DEEP, NF1),
+
+	/* GPP_F8 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F8, NONE),
+
+	/* GPP_F9 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F9, NONE),
+
+	/* GPP_F10 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_F10, 1, PLTRST),
+
+	/* GPP_F11 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F11, NONE),
+
+	/* GPP_F12 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F12, NONE),
+
+	/* GPP_F13 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F13, NONE),
+
+	/* GPP_F14 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F14, NONE),
+
+	/* GPP_F15 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F15, NONE),
+
+	/* GPP_F16 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F16, NONE),
+
+	/* GPP_F17 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F17, NONE),
+
+	/* GPP_F18 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F18, NONE),
+
+	/* GPP_F19 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F19, NONE),
+
+	/* GPP_F20 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F20, NONE),
+
+	/* GPP_F21 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F21, NONE),
+
+	/* GPP_F22 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_F22, NONE),
+
+	/* GPP_F23 - A4WP_PRESENT */
+	/* DW0: 0x44000700, DW1: 0x00001000 */
+	PAD_CFG_NF(GPP_F23, DN_20K, DEEP, NF1),
/* ------- GPIO Group GPP_H ------- */
-	_PAD_CFG_STRUCT(GPP_H0,  0x44000300, 0x3000),	/* I2S2_SCLK           */
-	_PAD_CFG_STRUCT(GPP_H1,  0x44000f00, 0x3000),	/* CNV_RF_RESET#       */
-	_PAD_CFG_STRUCT(GPP_H2,  0x84000f00, 0x3000),	/* MODEM_CLKREQ        */
-	_PAD_CFG_STRUCT(GPP_H3,  0x84000300, 0x3000),	/* I2S2_RXD            */
-	_PAD_CFG_STRUCT(GPP_H4,  0x84000300, 0x0000),	/* I2C2_SDA            */
-	_PAD_CFG_STRUCT(GPP_H5,  0x84000300, 0x0000),	/* I2C2_SCL            */
-	_PAD_CFG_STRUCT(GPP_H6,  0x84000702, 0x0000),	/* I2C3_SDA            */
-	_PAD_CFG_STRUCT(GPP_H7,  0x84000702, 0x0000),	/* I2C3_SCL            */
-	_PAD_CFG_STRUCT(GPP_H8,  0x84000702, 0x0000),	/* I2C4_SDA            */
-	_PAD_CFG_STRUCT(GPP_H9,  0x84000702, 0x0000),	/* I2C4_SCL            */
-	_PAD_CFG_STRUCT(GPP_H10, 0x84000603, 0x0000),	/* I2C5_SDA            */
-	_PAD_CFG_STRUCT(GPP_H11, 0x84000603, 0x0000),	/* I2C5_SCL            */
-	_PAD_CFG_STRUCT(GPP_H12, 0x84000201, 0x0000),	/* M2_SKT2_CFG0        */
-	_PAD_CFG_STRUCT(GPP_H13, 0x84000201, 0x0000),	/* M2_SKT2_CFG1        */
-	_PAD_CFG_STRUCT(GPP_H14, 0x84000200, 0x0000),	/* M2_SKT2_CFG2        */
-	_PAD_CFG_STRUCT(GPP_H15, 0x84000201, 0x0000),	/* M2_SKT2_CFG3        */
-	_PAD_CFG_STRUCT(GPP_H16, 0x84000201, 0x0000),	/* GPIO                */
-	_PAD_CFG_STRUCT(GPP_H17, 0x84000201, 0x0000),	/* GPIO                */
-	_PAD_CFG_STRUCT(GPP_H18, 0x84000700, 0x0000),	/* CPU_C10_GATE#       */
-	_PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x0000),	/* TIME_SYNC0          */
-	_PAD_CFG_STRUCT(GPP_H20, 0x84000300, 0x0000),	/* IMGCLKOUT1          */
-	_PAD_CFG_STRUCT(GPP_H21, 0x84000200, 0x0000),	/* GPIO                */
-	_PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x0000),	/* GPIO                */
-	_PAD_CFG_STRUCT(GPP_H23, 0x84000200, 0x0000),	/* GPIO                */
+	/* GPP_H0 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00003000 */
+	PAD_NC(GPP_H0, UP_20K),
+
+	/* GPP_H1 - CNV_RF_RESET# */
+	/* DW0: 0x44000f00, DW1: 0x00003000 */
+	PAD_CFG_NF(GPP_H1, UP_20K, DEEP, NF3),
+
+	/* GPP_H2 - MODEM_CLKREQ */
+	/* DW0: 0x44000f00, DW1: 0x00003000 */
+	PAD_CFG_NF(GPP_H2, UP_20K, DEEP, NF3),
+
+	/* GPP_H3 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00003000 */
+	PAD_NC(GPP_H3, UP_20K),
+
+	/* GPP_H4 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_H4, NONE),
+
+	/* GPP_H5 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_H5, NONE),
+
+	/* GPP_H6 - I2C3_SDA */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+
+	/* GPP_H7 - I2C3_SCL */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+
+	/* GPP_H8 - I2C4_SDA */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
+
+	/* GPP_H9 - I2C4_SCL */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
+
+	/* GPP_H10 - I2C5_SDA */
+	/* DW0: 0x84000603, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF1),
+
+	/* GPP_H11 - I2C5_SCL */
+	/* DW0: 0x84000603, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF1),
+
+	/* GPP_H12 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_H12, 1, PLTRST),
+
+	/* GPP_H13 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_H13, 1, PLTRST),
+
+	/* GPP_H14 - GPIO */
+	/* DW0: 0x84000200, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_H14, 0, PLTRST),
+
+	/* GPP_H15 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_H15, 1, PLTRST),
+
+	/* GPP_H16 - GPIO */
+	/* DW0: 0x04000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_H16, 1, RSMRST),
+
+	/* GPP_H17 - GPIO */
+	/* DW0: 0x04000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_H17, 1, RSMRST),
+
+	/* GPP_H18 - CPU_C10_GATE# */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+
+	/* GPP_H19 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_H19, 1, PLTRST),
+
+	/* GPP_H20 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_H20, NONE),
+
+	/* GPP_H21 - GPIO */
+	/* DW0: 0x44000200, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_H21, 0, DEEP),
+
+	/* GPP_H22 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_H22, 1, PLTRST),
+
+	/* GPP_H23 - GPIO */
+	/* DW0: 0x44000200, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_H23, 0, DEEP),
+
+	/* ------- GPIO Community 2 ------- */
/* ------- GPIO Group GPD ------- */
-	_PAD_CFG_STRUCT(GPD0,  0x44000702, 0x0000),	/* BATLOW#             */
-	_PAD_CFG_STRUCT(GPD1,  0x44000702, 0x3c00),	/* ACPRESENT           */
-	_PAD_CFG_STRUCT(GPD2,  0x44000702, 0x3c00),	/* LAN_WAKE#           */
-	_PAD_CFG_STRUCT(GPD3,  0x44000702, 0x3000),	/* PRWBTN#             */
-	_PAD_CFG_STRUCT(GPD4,  0x44000600, 0x0000),	/* SLP_S3#             */
-	_PAD_CFG_STRUCT(GPD5,  0x44000600, 0x0000),	/* SLP_S4#             */
-	_PAD_CFG_STRUCT(GPD6,  0x44000600, 0x0000),	/* SLP_A#              */
-	_PAD_CFG_STRUCT(GPD7,  0x44000200, 0x0000),	/* GPIO                */
-	_PAD_CFG_STRUCT(GPD8,  0x44000700, 0x0000),	/* SUSCLK              */
-	_PAD_CFG_STRUCT(GPD9,  0x44000700, 0x0000),	/* SLP_WLAN#           */
-	_PAD_CFG_STRUCT(GPD10, 0x44000600, 0x0000),	/* SLP_S5#             */
-	_PAD_CFG_STRUCT(GPD11, 0x44000600, 0x0000),	/* LANPHYPC            */
+	/* GPD0 - BATLOW# */
+	/* DW0: 0x04000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPD0, NONE, RSMRST, NF1),
+
+	/* GPD1 - ACPRESENT */
+	/* DW0: 0x04000702, DW1: 0x00003c00 */
+	PAD_CFG_NF(GPD1, NATIVE, RSMRST, NF1),
+
+	/* GPD2 - LAN_WAKE# */
+	/* DW0: 0x04000702, DW1: 0x00003c00 */
+	PAD_CFG_NF(GPD2, NATIVE, RSMRST, NF1),
+
+	/* GPD3 - PRWBTN# */
+	/* DW0: 0x04000702, DW1: 0x00003000 */
+	PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1),
+
+	/* GPD4 - SLP_S3# */
+	/* DW0: 0x04000600, DW1: 0x00000000 */
+	PAD_CFG_NF(GPD4, NONE, RSMRST, NF1),
+
+	/* GPD5 - SLP_S4# */
+	/* DW0: 0x04000600, DW1: 0x00000000 */
+	PAD_CFG_NF(GPD5, NONE, RSMRST, NF1),
+
+	/* GPD6 - SLP_A# */
+	/* DW0: 0x04000600, DW1: 0x00000000 */
+	PAD_CFG_NF(GPD6, NONE, RSMRST, NF1),
+
+	/* GPD7 - GPIO */
+	/* DW0: 0x04000200, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPD7, 0, RSMRST),
+
+	/* GPD8 - SUSCLK */
+	/* DW0: 0x04000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPD8, NONE, RSMRST, NF1),
+
+	/* GPD9 - SLP_WLAN# */
+	/* DW0: 0x04000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPD9, NONE, RSMRST, NF1),
+
+	/* GPD10 - SLP_S5# */
+	/* DW0: 0x04000600, DW1: 0x00000000 */
+	PAD_CFG_NF(GPD10, NONE, RSMRST, NF1),
+
+	/* GPD11 - LANPHYPC */
+	/* DW0: 0x04000600, DW1: 0x00000000 */
+	PAD_CFG_NF(GPD11, NONE, RSMRST, NF1),
+
+	/* ------- GPIO Community 4 ------- */
/* ------- GPIO Group GPP_C ------- */
-	_PAD_CFG_STRUCT(GPP_C0,  0x44000702, 0x0000),	/* SMBCLK              */
-	_PAD_CFG_STRUCT(GPP_C1,  0x44000702, 0x0000),	/* SMBDATA             */
-	_PAD_CFG_STRUCT(GPP_C2,  0x44000201, 0x0000),	/* SMBALERT#           */
-	_PAD_CFG_STRUCT(GPP_C3,  0x44000702, 0x0000),	/* SML0CLK             */
-	_PAD_CFG_STRUCT(GPP_C4,  0x44000702, 0x0000),	/* SML0DATA            */
-	_PAD_CFG_STRUCT(GPP_C5,  0x84000201, 0x0000),	/* SML0ALERT#          */
-	_PAD_CFG_STRUCT(GPP_C6,  0x44000300, 0x0000),	/* SML1CLK             */
-	_PAD_CFG_STRUCT(GPP_C7,  0x44000300, 0x0000),	/* SML1DATA            */
-	_PAD_CFG_STRUCT(GPP_C8,  0x84000201, 0x0000),	/* UART0_RXD           */
-	_PAD_CFG_STRUCT(GPP_C9,  0x84000201, 0x0000),	/* UART0_TXD           */
-	_PAD_CFG_STRUCT(GPP_C10, 0x84000200, 0x0000),	/* UART0_RTS#          */
-	_PAD_CFG_STRUCT(GPP_C11, 0x84000201, 0x0000),	/* UART0_CTS#          */
-	_PAD_CFG_STRUCT(GPP_C12, 0x84000603, 0x0000),	/* UART1_RXD           */
-	_PAD_CFG_STRUCT(GPP_C13, 0x84000700, 0x0000),	/* UART1_TXD           */
-	_PAD_CFG_STRUCT(GPP_C14, 0x84000700, 0x0000),	/* UART1_RTS#          */
-	_PAD_CFG_STRUCT(GPP_C15, 0x84000702, 0x0000),	/* UART1_CTS#          */
-	_PAD_CFG_STRUCT(GPP_C16, 0x84000402, 0x0000),	/* I2C0_SDA            */
-	_PAD_CFG_STRUCT(GPP_C17, 0x84000402, 0x0000),	/* I2C0_SCL            */
-	_PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0000),	/* I2C1_SDA            */
-	_PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0000),	/* I2C1_SCL            */
-	_PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x0000),	/* UART2_RXD           */
-	_PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x0000),	/* UART2_TXD           */
-	_PAD_CFG_STRUCT(GPP_C22, 0x84000201, 0x0000),	/* UART2_RTS#          */
-	_PAD_CFG_STRUCT(GPP_C23, 0x40100102, 0x1000),	/* UART2_CTS#          */
+	/* GPP_C0 - SMBCLK */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+
+	/* GPP_C1 - SMBDATA */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+
+	/* GPP_C2 - GPIO */
+	/* DW0: 0x44000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_C2, 1, DEEP),
+
+	/* GPP_C3 - SML0CLK */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
+
+	/* GPP_C4 - SML0DATA */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
+
+	/* GPP_C5 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_C5, 1, PLTRST),
+
+	/* GPP_C6 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_C6, NONE),
+
+	/* GPP_C7 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_C7, NONE),
+
+	/* GPP_C8 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_C8, 1, PLTRST),
+
+	/* GPP_C9 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_C9, 1, PLTRST),
+
+	/* GPP_C10 - GPIO */
+	/* DW0: 0x84000200, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_C10, 0, PLTRST),
+
+	/* GPP_C11 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_C11, 1, PLTRST),
+
+	/* GPP_C12 - UART1_RXD */
+	/* DW0: 0x84000603, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C12, NONE, PLTRST, NF1),
+
+	/* GPP_C13 - UART1_TXD */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
+
+	/* GPP_C14 - UART1_RTS# */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
+
+	/* GPP_C15 - UART1_CTS# */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1),
+
+	/* GPP_C16 - I2C0_SDA */
+	/* DW0: 0x84000402, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C16, NONE, PLTRST, NF1),
+
+	/* GPP_C17 - I2C0_SCL */
+	/* DW0: 0x84000402, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C17, NONE, PLTRST, NF1),
+
+	/* GPP_C18 - I2C1_SDA */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+
+	/* GPP_C19 - I2C1_SCL */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+
+	/* GPP_C20 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_C20, NONE),
+
+	/* GPP_C21 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_C21, NONE),
+
+	/* GPP_C22 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_C22, 1, PLTRST),
+
+	/* GPP_C23 - GPIO */
+	/* DW0: 0x40100102, DW1: 0x00001000 */
+	PAD_CFG_GPI_APIC(GPP_C23, DN_20K, DEEP, LEVEL, NONE),
/* ------- GPIO Group GPP_E ------- */
-	_PAD_CFG_STRUCT(GPP_E0,  0x84000300, 0x0000),	/* SATAXPCIE0          */
-	_PAD_CFG_STRUCT(GPP_E1,  0x84000300, 0x0000),	/* SATAXPCIE1          */
-	_PAD_CFG_STRUCT(GPP_E2,  0x84000502, 0x3000),	/* SATAXPCIE2          */
-	_PAD_CFG_STRUCT(GPP_E3,  0x82040102, 0x0000),	/* CPU_GP0             */
-	_PAD_CFG_STRUCT(GPP_E4,  0x84000201, 0x0000),	/* SATA_DEVSLP0        */
-	_PAD_CFG_STRUCT(GPP_E5,  0x84000300, 0x0000),	/* SATA_DEVSLP1        */
-	_PAD_CFG_STRUCT(GPP_E6,  0x84000300, 0x0000),	/* SATA_DEVSLP2        */
-	_PAD_CFG_STRUCT(GPP_E7,  0x82000102, 0x0000),	/* CPU_GP1             */
-	_PAD_CFG_STRUCT(GPP_E8,  0x84000700, 0x0000),	/* SATALED#            */
-	_PAD_CFG_STRUCT(GPP_E9,  0x44001700, 0x0000),	/* USB2_OC0#            */
-	_PAD_CFG_STRUCT(GPP_E10, 0x44001700, 0x0000),	/* USB2_OC1#            */
-	_PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0000),	/* USB2_OC2#           */
-	_PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x0000),	/* USB2_OC3#           */
-	_PAD_CFG_STRUCT(GPP_E13, 0x84000700, 0x0000),	/* DDPB_HPD0           */
-	_PAD_CFG_STRUCT(GPP_E14, 0x84000702, 0x0000),	/* DDPC_HPD1           */
-	_PAD_CFG_STRUCT(GPP_E15, 0x84000201, 0x0000),	/* DDPD_HPD2           */
-	_PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x3000),	/* GPIO                */
-	_PAD_CFG_STRUCT(GPP_E17, 0x84000700, 0x0000),	/* EDP_HPD             */
-	_PAD_CFG_STRUCT(GPP_E18, 0x84000702, 0x0000),	/* DPPB_CTRLCLK        */
-	_PAD_CFG_STRUCT(GPP_E19, 0x84000602, 0x0000),	/* DPPB_CTRLDATA       */
-	_PAD_CFG_STRUCT(GPP_E20, 0x84000700, 0x0000),	/* DPPC_CTRLCLK        */
-	_PAD_CFG_STRUCT(GPP_E21, 0x84000602, 0x0000),	/* DPPC_CTRLDATA       */
-	_PAD_CFG_STRUCT(GPP_E22, 0x84000702, 0x0000),	/* DPPD_CTRLCLK        */
-	_PAD_CFG_STRUCT(GPP_E23, 0x84000602, 0x0000),	/* DPPD_CTRLDATA       */
+	/* GPP_E0 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_E0, NONE),
+	/* GPP_E1 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_E1, NONE),
+
+	/* GPP_E2 - SATAXPCIE2 */
+	/* DW0: 0x84000502, DW1: 0x00003000 */
+	PAD_CFG_NF(GPP_E2, UP_20K, PLTRST, NF1),
+
+	/* GPP_E3 - GPIO */
+	/* DW0: 0x82040102, DW1: 0x00000000 */
+	PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE),
+
+	/* GPP_E4 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_E4, 1, PLTRST),
+
+	/* GPP_E5 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_E5, NONE),
+
+	/* GPP_E6 - GPIO */
+	/* DW0: 0x44000300, DW1: 0x00000000 */
+	PAD_NC(GPP_E6, NONE),
+
+	/* GPP_E7 - GPIO */
+	/* DW0: 0x82000102, DW1: 0x00000000 */
+	PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, PLTRST, EDGE_SINGLE, ACPI),
+
+	/* GPP_E8 - SATALED# */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),
+
+	/* GPP_E9 - RESERVED */
+	/* DW0: 0x44001700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF5),
+
+	/* GPP_E10 - RESERVED */
+	/* DW0: 0x44001700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF5),
+
+	/* GPP_E11 - USB2_OC2# */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+
+	/* GPP_E12 - USB2_OC3# */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+
+	/* GPP_E13 - DDPB_HPD0 */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+
+	/* GPP_E14 - DDPC_HPD1 */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+
+	/* GPP_E15 - GPIO */
+	/* DW0: 0x84000201, DW1: 0x00000000 */
+	PAD_CFG_GPO(GPP_E15, 1, PLTRST),
+
+	/* GPP_E16 - GPIO */
+	/* DW0: 0x80880102, DW1: 0x00003000 */
+	PAD_CFG_GPI_SCI(GPP_E16, UP_20K, PLTRST, LEVEL, INVERT),
+
+	/* GPP_E17 - EDP_HPD */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+
+	/* GPP_E18 - DPPB_CTRLCLK */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
+
+	/* GPP_E19 - DPPB_CTRLDATA */
+	/* DW0: 0x44000602, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
+
+	/* GPP_E20 - DPPC_CTRLCLK */
+	/* DW0: 0x44000700, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
+
+	/* GPP_E21 - DPPC_CTRLDATA */
+	/* DW0: 0x44000602, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+
+	/* GPP_E22 - DPPD_CTRLCLK */
+	/* DW0: 0x44000702, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
+
+	/* GPP_E23 - DPPD_CTRLDATA */
+	/* DW0: 0x44000602, DW1: 0x00000000 */
+	PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
 };
const struct pad_config *variant_gpio_table(size_t *num)
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I6ac747ad4e650c24d2b7e34228ff74140c51a0c1
Gerrit-Change-Number: 44503
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier matt.devillier@gmail.com
Gerrit-MessageType: newchange



    