[S] Change in coreboot[master]: soc/intel/common/block/pcie/rtd3: Fix source clock check condition fo...

[Cliff Huang (Code Review)]

Attention is currently required from: Bora Guvendik, Hannah Williams, Anil Kumar K, Cliff Huang, Tarun Tuli.

Hello Bora Guvendik, Hannah Williams, Anil Kumar K, build bot (Jenkins), Tarun Tuli, Jérémy Compostella,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/73889

to look at the new patch set (#4).

Change subject: soc/intel/common/block/pcie/rtd3: Fix source clock check condition for PM method
......................................................................

soc/intel/common/block/pcie/rtd3: Fix source clock check condition for PM method

srcclk_pin is 0-based and '0' is a valid clock source number. If
srcclk_pin is set to -1, then the clock will not be disabled in D3.
Therefore, clock source gating method should not be generated.

BUG=b:271003060
BRANCH=firmware-brya-14505.B
TEST=Boot to OS and check that rtd3 ACPI entries are generated as
expected. For those PCI devices with RTD3 driver whose srcclk_pin to
0, the RTD3 entries should not be missing due to check error.

Signed-off-by: Cliff Huang 
Change-Id: Ia831b8fd17572cc35765bd226d1db470f12ddd41
---
M src/soc/intel/common/block/pcie/rtd3/rtd3.c
1 file changed, 23 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/73889/4