Attention is currently required from: Bora Guvendik, Cliff Huang, Jamie Ryu, Jérémy Compostella, Paul Menzel, Saurabh Mishra, Wonkyu Kim.
Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/83981?usp=email )
Change subject: soc/intel/common/gpio: support 16-bit CPU Port ID
......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/c/coreboot/+/83981/comment/5b54d17c_abf82f6f?usp... :
PS4, Line 1071: }
This condition is to find the the pad from a range & it's offset from the first pad and returns false if not found.
start_pos will take care of PTL community 5 group B:
GPP_B_00: vw_base = 10h start pos = 3
Also, vw_map[i].base will take care of the jumped base and start_pos such as group D in community 5:
...
GPP_B_25: 13h 1
GPP_D_00: 14h 0 <- not continue to use vw_base 13h start = 2.
...
In PTL SOC, this is added to pint to comm5 .vw_map:
static const struct vw_map ptl_community5_vw_map[] = {
{0x10, 3},
{0x14, 0},
};
Also, in community 3:
...
GPP_A_17: 12h 1
GPP_H_00: 13h 0 <- not continue with vw_base 12h start_pos = 2
...
This is added to point to comm5 .vw_map
static const struct vw_map ptl_community3_vw_map[] = {
{0x10, 0},
{0x13, 0},
};
sure looking forward for the EDS update . Please help to prioritize that as well.
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