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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63640
to look at the new patch set (#5).
Change subject: soc/intel/common/smbus: Add `finalize` operation for smbus ......................................................................
soc/intel/common/smbus: Add `finalize` operation for smbus
This patch implements the required operations to perform prior to booting to OS using coreboot native driver when platform decides to skip FSP notify APIs i.e. Post PCI Enumeration.
The smbus `.final` operation ensures locking the TCO register when coreboot decides to skip FspNotifyApi() calls.
BUG=b:211954778 TEST=Able to build google/brya with these changes and coreboot log with this code change as below with ADL SoC skip calling into FspNotifyAPIs:
[INFO ] Finalize devices... [DEBUG] PCI: 00:1f.4 final
localhost ~ # lspci -xxx | less
00:1f.4 Intel Corporation Alder Lake PCH-P SMBus Host Controller (rev 01)
Offset 8, Bit 12 a.k.a TCO Lock bit is set (meaning locked).
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: Ie945680049514e6c5d797790a381a6946e836926 --- M src/soc/intel/common/block/smbus/smbus.c 1 file changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/63640/5