[XL] Change in coreboot[main]: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock

[Subrata Banik (Code Review)]

Attention is currently required from: Ashish Kumar Mishra, Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Felix Singer, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Saurabh Mishra, Tarun.

Subrata Banik has posted comments on this change by Saurabh Mishra. ( https://review.coreboot.org/c/coreboot/+/83354?usp=email )

Change subject: soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
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Patch Set 45:

(2 comments)

File src/soc/intel/pantherlake/Kconfig:

https://review.coreboot.org/c/coreboot/+/83354/comment/1e8406c9_f5a5a55f?usp... :
PS36, Line 133: 10
> Hi, as per EDS v0.7 #815002, chapter 21.0, support for up
> to 8 USB 2.0.
> I am not able to find the doc "731941".

8 is for PTL-P I believe for PTL-U, it's 6 if i'm not wrong as per Intel doc.

For now, keep 8 as we aee going to work on PTL-UH (P).

File src/soc/intel/pantherlake/include/soc/iomap.h:

https://review.coreboot.org/c/coreboot/+/83354/comment/1dae2d57_2bb7084a?usp... :
PS32, Line 19: #define SAF_BASE_ADDRESS	0xfa000000
> Hi Subrata, due to document v1.1 is not released externally yet, i am working with Intel internal team to make it sharebale over corsbug. Meanwhile, can we add "TO-DO" comment to the SAF Addr, and unblock this patch?

I don't understand what you mean by unblocking this CL. I won't be able to merge any CL unless the upper layer mainboard CL is V+1. Please continue adding other CLs and hopefully this doc reaches me in time.