[L] Change in coreboot[main]: src/mainboard/intel/frost_creek: add a new CRB Frost Creek for SNR
yuchi.chen@intel.com has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83322?usp=email )
Change subject: src/mainboard/intel/frost_creek: add a new CRB Frost Creek for SNR ......................................................................
src/mainboard/intel/frost_creek: add a new CRB Frost Creek for SNR
Change-Id: If3b387a6a4a567415aef21e520056c23b8cfa013 Signed-off-by: Yuchi Chen yuchi.chen@intel.com --- A src/mainboard/intel/frost_creek/COPYING-NOTICE A src/mainboard/intel/frost_creek/Kconfig A src/mainboard/intel/frost_creek/Kconfig.name A src/mainboard/intel/frost_creek/Makefile.mk A src/mainboard/intel/frost_creek/acpi/mainboard.asl A src/mainboard/intel/frost_creek/acpi/platform.asl A src/mainboard/intel/frost_creek/acpi_tables.c A src/mainboard/intel/frost_creek/board.fmd A src/mainboard/intel/frost_creek/board_id.c A src/mainboard/intel/frost_creek/board_id.h A src/mainboard/intel/frost_creek/board_info.txt A src/mainboard/intel/frost_creek/devicetree.cb A src/mainboard/intel/frost_creek/dsdt.asl A src/mainboard/intel/frost_creek/gpio.inc A src/mainboard/intel/frost_creek/ramstage.c A src/mainboard/intel/frost_creek/ramstage.h A src/mainboard/intel/frost_creek/romstage.c A src/mainboard/intel/frost_creek/romstage.h 18 files changed, 676 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/83322/1
diff --git a/src/mainboard/intel/frost_creek/COPYING-NOTICE b/src/mainboard/intel/frost_creek/COPYING-NOTICE new file mode 100644 index 0000000..0e1018c --- /dev/null +++ b/src/mainboard/intel/frost_creek/COPYING-NOTICE @@ -0,0 +1,16 @@ +NOTICE + +This software specifically enables pre-production +hardware provided by Intel Corporation. The terms +describing your rights and responsibilities to use +such hardware are covered by a separate evaluation +agreement. Of specific note in that agreement is +the requirement that you do not release or publish +information on the hardware without the specific +written authorization of Intel Corporation. + +Intel Corporation requests that you do not +release, publish, or distribute this software +until you are specifically authorized. These +terms are deleted upon publication of this +software. diff --git a/src/mainboard/intel/frost_creek/Kconfig b/src/mainboard/intel/frost_creek/Kconfig new file mode 100644 index 0000000..2aee2a9 --- /dev/null +++ b/src/mainboard/intel/frost_creek/Kconfig @@ -0,0 +1,30 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_INTEL_FROST_CREEK + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_SNOWRIDGE + select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + default "intel/frost_creek" if BOARD_INTEL_FROST_CREEK + +config MAINBOARD_PART_NUMBER + default "Frost Creek" if BOARD_INTEL_FROST_CREEK + +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config CBFS_SIZE + default 0xc00000 + +config DIMM_MAX + default 4 + +config DIMM_SPD_SIZE + default 512 + +endif # BOARD_INTEL_FROST_CREEK diff --git a/src/mainboard/intel/frost_creek/Kconfig.name b/src/mainboard/intel/frost_creek/Kconfig.name new file mode 100644 index 0000000..384e9df --- /dev/null +++ b/src/mainboard/intel/frost_creek/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_FROST_CREEK + bool "Frost Creek" diff --git a/src/mainboard/intel/frost_creek/Makefile.mk b/src/mainboard/intel/frost_creek/Makefile.mk new file mode 100644 index 0000000..218f39f --- /dev/null +++ b/src/mainboard/intel/frost_creek/Makefile.mk @@ -0,0 +1,9 @@ +## SPDX-License-Identifier: GPL-2.0-only + +romstage-y += board_id.c +romstage-y += romstage.c + +ramstage-y += board_id.c +ramstage-y += ramstage.c + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/ diff --git a/src/mainboard/intel/frost_creek/acpi/mainboard.asl b/src/mainboard/intel/frost_creek/acpi/mainboard.asl new file mode 100644 index 0000000..160fbb7 --- /dev/null +++ b/src/mainboard/intel/frost_creek/acpi/mainboard.asl @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (_SB) +{ + Device (PWRB) + { + Name(_HID, EisaId("PNP0C0C")) + + // Wake + Name(_PRW, Package(){0x1d, 0x05}) + } +} diff --git a/src/mainboard/intel/frost_creek/acpi/platform.asl b/src/mainboard/intel/frost_creek/acpi/platform.asl new file mode 100644 index 0000000..cee5ea8 --- /dev/null +++ b/src/mainboard/intel/frost_creek/acpi/platform.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// IO-Trap at 0x800. This is the ACPI->SMI communication interface. +OperationRegion (IO_T, SystemIO, 0x800, 0x10) +Field (IO_T, ByteAcc, NoLock, Preserve) +{ + Offset (0x8), + TRP0, 8 // IO-Trap at 0x808 +} + +/* The APM port can be used for generating software SMIs. */ +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* SMI I/O Trap. */ +Method (TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} diff --git a/src/mainboard/intel/frost_creek/acpi_tables.c b/src/mainboard/intel/frost_creek/acpi_tables.c new file mode 100644 index 0000000..b6e3846 --- /dev/null +++ b/src/mainboard/intel/frost_creek/acpi_tables.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; +} diff --git a/src/mainboard/intel/frost_creek/board.fmd b/src/mainboard/intel/frost_creek/board.fmd new file mode 100644 index 0000000..bf89671 --- /dev/null +++ b/src/mainboard/intel/frost_creek/board.fmd @@ -0,0 +1,9 @@ +FLASH@0xfe000000 0x02000000 { + BIOS@0x01400000 0x00C00000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE@0x10000 0x40000 + RW_KTI_CACHE@0x50000 0x1000 + FMAP@0x51000 0x200 + COREBOOT(CBFS)@0x51200 0x00baee00 + } +} diff --git a/src/mainboard/intel/frost_creek/board_id.c b/src/mainboard/intel/frost_creek/board_id.c new file mode 100644 index 0000000..a9d3049 --- /dev/null +++ b/src/mainboard/intel/frost_creek/board_id.c @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boardid.h> +#include <console/console.h> + +#include "board_id.h" + +uint32_t board_id(void) +{ + printk(BIOS_SPEW, "Board ID: 0x%x\n", BOARD_ID_FROST_CREEK); + + return BOARD_ID_FROST_CREEK; +} diff --git a/src/mainboard/intel/frost_creek/board_id.h b/src/mainboard/intel/frost_creek/board_id.h new file mode 100644 index 0000000..7a68474 --- /dev/null +++ b/src/mainboard/intel/frost_creek/board_id.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MAINBOARD_FROST_CREEK_BOARD_ID_H_ +#define _MAINBOARD_FROST_CREEK_BOARD_ID_H_ + +#define BOARD_ID_FROST_CREEK 0x52 + +#endif // _MAINBOARD_FROST_CREEK_BOARD_ID_H_ diff --git a/src/mainboard/intel/frost_creek/board_info.txt b/src/mainboard/intel/frost_creek/board_info.txt new file mode 100644 index 0000000..1b338ab --- /dev/null +++ b/src/mainboard/intel/frost_creek/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Frost Creek +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/frost_creek/devicetree.cb b/src/mainboard/intel/frost_creek/devicetree.cb new file mode 100644 index 0000000..9de2ff4 --- /dev/null +++ b/src/mainboard/intel/frost_creek/devicetree.cb @@ -0,0 +1,193 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/snowridge + + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on end + + device domain 0 on #S0 personality:1 (UBOX_IIO - legacy) + # + # S0 hosts all the PCH peripherals and some of the CPU Complex peripherals + # (for example, DMA controller and CPU Complex Intel® Trace Hub) + # + device pci 00.0 on end # 0x09a2 - Mesh2IIO MMAP/Intel VT-d - Bus S0 + device pci 00.1 on end # 0x09a4 - Mesh2IIO PMU/PMON - Bus S0 + device pci 00.2 on end # 0x09a3 - Mesh2IIO RAS - Bus S0 + device pci 00.3 on end # 0x09a5 - Mesh2IIO DFx - Bus S0 + device pci 00.4 on end # 0x0998 - Satellite IEH - Bus S0 +#not found device pci 00.5 off end # 0x28c0 -VMD - Bus S0 (Volume Management Device) + device pci 01.0 on end # 0x0b00 - DMA Channel 0 + device pci 01.1 on end # 0x0b00 - DMA Channel 1 + device pci 01.2 on end # 0x0b00 - DMA Channel 2 + device pci 01.3 on end # 0x0b00 - DMA Channel 3 + device pci 01.4 on end # 0x0b00 - DMA Channel 4 + device pci 01.5 on end # 0x0b00 - DMA Channel 5 + device pci 01.6 on end # 0x0b00 - DMA Channel 6 + device pci 01.7 on end # 0x0b00 - DMA Channel 7 + device pci 02.0 on end # 0x09a7 - PECI Out-Of-Band Management Services Module (OOBMSM) + device pci 02.1 on end # 0x09a7 - PECI OOB-MSM - Discovery + device pci 02.2 on end # 0x09a7 - PECI OOB-MSM - Design for Debug (DFD) + device pci 02.4 on end # 0x3456 - CPU Complex Intel Trace Hub + device pci 07.0 on end # 0x18b3 - SATA Controller 0 +# let`s coreboot device pci 09.0 on end # 0x18a4 - PCH PCIe Cluster 0, Root Port 0 +# autodetect when device pci 0a.0 on end # 0x18a5 - PCH PCIe Cluster 0, Root Port 1 +# something is device pci 0b.0 on end # 0x18a6 - PCH PCIe Cluster 0, Root Port 2 +# plugged in device pci 0c.0 on end # 0x18a7 - PCH PCIe Cluster 0, Root Port 3 + device pci 0e.0 on end # 0x18f3 - SATA Controller 2 + device pci 0f.0 on end # 0x18ac - SMBus gen - Host (DMA) SMBus +# let`s coreboot device pci 14.0 on end # 0x18ad - PCH PCIe Cluster 2, Root Port 8 +# autodetect when device pci 15.0 on end # 0x18ae - PCH PCIe Cluster 2, Root Port 9 +# something is device pci 16.0 on end # 0x18af - PCH PCIe Cluster 2, Root Port 10 +# plugged in device pci 17.0 on end # 0x18a2 - PCH PCIe Cluster 2, Root Port 11 + device pci 18.0 on end # 0x18d3 - Intel ME - HECI 1 + device pci 18.1 on end # 0x18d4 - Intel ME - HECI 2 + device pci 18.2 hidden end # 0x18ea - Intel ME - IDER + device pci 18.3 hidden end + device pci 18.4 on end # 0x18d6 - Intel ME - HECI 3 + device pci 18.6 hidden end # 0x18d7 - Intel ME - HECI 4 + device pci 1a.0 on end # 0x18d8 - HSUART 0 + device pci 1a.1 on end # 0x18d8 - HSUART 1 + device pci 1a.2 on end # 0x18d8 - HSUART 2 + device pci 1a.3 on end # 0x18d9 - Intel ME MROM +#not found device pci 1a.4 on end # 0x18ec - Reserved +#not found device pci 1b.0 on end # 0x18e5 - Reserved +#not found device pci 1b.1 on end # 0x18e6 - Reserved +#not found device pci 1b.2 on end # 0x18e7 - Reserved +#not found device pci 1b.3 on end # 0x18e8 - Reserved +#not found device pci 1b.4 on end # 0x18e9 - Reserved +#not found device pci 1b.6 on end # 0x18eb - Reserved + device pci 1c.0 on end # 0x18db - eMMC Controler + device pci 1d.0 on end # 0x0998 - Satellite IEH - PCH + device pci 1e.0 on end # 0x18d0 - USB Controller +#not found device pci 1e.2 on end # 0x18e3 - PCM/SRAM + device pci 1f.0 on end # 0x18dc - LPC/eSPI Controller + device pci 1f.1 on end # 0x18dd - PH Bridge Control - P2SB + device pci 1f.2 hidden end # 0x18de - PCH PMC + device pci 1f.4 on end # 0x18df - Legacy SMBus + device pci 1f.5 on end # 0x18e0 - SPI Controller + device pci 1f.7 on end # 0x18e1 - PCH Intel® Trace Hub + end # D0 S0 + device domain 1 on #S1 personality:1 (UBOX_IIO) + # + # S1 hosts the CPU Complex PCIe Root Ports + # + device pci 00.0 on end # 0x09a2 - Mesh2IIO MMAP/Intel VT-d - Bus S1 + device pci 00.1 on end # 0x09a4 - Mesh2IIO PMU/PMON - Bus S1 + device pci 00.2 on end # 0x09a3 - Mesh2IIO RAS - Bus S1 + device pci 00.3 on end # 0x09a5 - Mesh2IIO DFx - Bus S1 + device pci 00.4 on end # 0x0998 - Satellite IEH - Bus S1 +#not found device pci 00.5 off end # 0x28c0 - Bus S1 (Volume Management Device) +# let`s coreboot device pci 04.0 on end # 0x334a - CPU PCIe Root Port - A link widths: x16, x8, x4, x2, x1 +# autodetect when device pci 05.0 on end # 0x334b - CPU PCIe Root Port - B link widths: x4, x2, x1 +# something is device pci 06.0 on end # 0x334c - CPU PCIe Root Port - C link widths: x8, x4, x2, x1 +# plugged in device pci 07.0 on end # 0x334d - CPU PCIe Root Port - D link widths: x4, x2, x1 + end # D1 S1 + device domain 2 on #S2 personality:5 (NAC) + # + # S2 hosts the Virtual Root Port (VRP) to the Intel® QAT v1.8 accelerator, + # the Intel® QAT v1.8 accelerator, and the iRC-NAC + # + device pci 00.0 on end # 0x09a2 - Mesh2IIO MMAP/Intel VT-d - Bus S2 + device pci 00.1 on end # 0x09a4 - Mesh2IIO PMU/PMON - Bus S2 + device pci 00.2 on end # 0x09a3 - Mesh2IIO RAS - Bus S2 + device pci 00.3 on end # 0x09a5 - Mesh2IIO DFx - Bus S2 + device pci 00.4 on end # 0x0998 - Satellite IEH - Bus S2 +#not found device pci 00.5 off end # 0x28c0 - VMD - Bus S2 (Volume Management Device) +#not found device pci 05.0 on # 0x18da - Virtual Root Port to Intel QAT v1.8 accelerator +#not found device pci 00.0 on end # 0x18a0 - Intel QAT v1.8 accelerator +#not found end + end # D2 S2 + device domain 3 on #S3 personality:5 (NAC) + # + # S3 hosts the VRP to the Network Interface and Scheduler (NIS) and the NIS + # + device pci 00.0 on end # 0x09a2 - Mesh2IIO MMAP/Intel VT-d - Bus S3 + device pci 00.1 on end # 0x09a4 - Mesh2IIO PMU/PMON - Bus S3 + device pci 00.2 on end # 0x09a3 - Mesh2IIO RAS - Bus S3 + device pci 00.3 on end # 0x09a5 - Mesh2IIO DFx - Bus S3 + device pci 00.4 on end # 0x0998 - Satellite IEH - Bus S3 +#not found device pci 00.5 off end # 0x28c0 - VMD - Bus S3 (Volume Management Device) + device pci 04.0 on # 0x18d1 - Virtual Root Port to Network Interface and Scheduler (NIS) + # device pci 00.0 on end # 0x1896 - NIS - 100 Gb/s + # 0x189c - NIS - 50Gb/s + device pci 00.0 on end # 0x1891 - NIS + device pci 00.1 on end # 0x1891 - NIS + device pci 00.2 on end # 0x1891 - NIS + device pci 00.3 on end # 0x1891 - NIS + device pci 00.4 on end # 0x1892 - NIS + device pci 00.5 on end # 0x1892 - NIS + device pci 00.6 on end # 0x1892 - NIS + device pci 00.7 on end # 0x1892 - NIS + end + end # D3 S3 + device domain 4 on #S4 personality:5 (NAC) + # + # S4 hosts the Hardware Queue Manager (HQM) accelerator + # + device pci 00.0 on end # 0x09a2 - Mesh2IIO MMAP/Intel VT-d - Bus S4 + device pci 00.1 on end # 0x09a4 - Mesh2IIO PMU/PMON - Bus S4 + device pci 00.2 on end # 0x09a3 - Mesh2IIO RAS - Bus S4 + device pci 00.3 on end # 0x09a5 - Mesh2IIO DFx - Bus S4 + device pci 00.4 on end # 0x0998 - Satellite IEH - Bus S4 +#not found device pci 00.5 off end # 0x28c0 - VMD - Bus S4 (Volume Management Device) + device pci 05.0 on # 0x18da - Virtual Root Port to Intel QAT v1.8 accelerator + device pci 00.0 on end # 0x18a0 - Intel QAT v1.8 accelerator + end + device pci 06.0 on end # 0x18e2 - iRC-NAC + end # D4 S4 + device domain 5 off #personality:0x18 (Unused) + end # D5 S5 + device domain 6 off #personality:8 (Reserved) + end # D6 S6 + device domain 7 on #personality:0 (Ubox)U0 + # + # U0 is the second-highest bus number assigned to the device + # U0 hosts the Ubox, Serial Presence Detect (SPD) SMBus, + # Virtual Pin Port (VPP) SMBus, the Memory Controller, and DDRIO + # + device pci 00.0 on end # 0x3460 - Ubox - Noncoherent Events (NCEVENTS) + device pci 00.1 on end # 0x3451 - Ubox - Register Access Control Unit (RACU) + device pci 00.2 on end # 0x3452 - Ubox - Noncoherent Decode (NCDECS) + device pci 00.3 on end # 0x0998 - Ubox - Global I/O Error Handler (Global IEH) + device pci 00.5 on end # 0x3455 - Ubox - Error Handling + device pci 0b.0 on end # 0x3448 - Ubox - Serial Presence Detect (SPD) SMBus + device pci 0b.1 on end # 0x3449 - Ubox - ???? + device pci 0b.2 on end # 0x344b - Ubox - CPU Complex Virtual Pin Port (VPP) SMBus + device pci 0c.0 on end # 0x344a - Ubox - IMC + device pci 1a.0 on end # 0x2880 - Ubox - DDRIO + end # D7 U0 + device domain 8 on #U1 - additional root bus 0xFF for domain/stack 7 + # + # U1 is the highest bus number assigned to the device + # U1 hosts the Cache and Home Agent (CHA) and Power Control Unit (PCU) + # + device pci 00.0 on end # 0x344c - CHA0_GRP1 - Mesh Credit Configuration + device pci 00.1 on end # 0x344c - CHA1_GRP1 - Mesh Credit Configuration + device pci 00.2 on end # 0x344c - CHA2_GRP1 - Mesh Credit Configuration + device pci 00.3 on end # 0x344c - CHA3_GRP1 - Mesh Credit Configuration + device pci 00.4 on end # 0x344c - CHA4_GRP1 - Mesh Credit Configuration + device pci 00.5 on end # 0x344c - CHA5_GRP1 - Mesh Credit Configuration + device pci 0a.0 on end # 0x344d - CHA0_GRP0 - Mesh Credit Configuration + device pci 0a.1 on end # 0x344d - CHA1_GRP0 - Mesh Credit Configuration + device pci 0a.2 on end # 0x344d - CHA2_GRP0 - Mesh Credit Configuration + device pci 0a.3 on end # 0x344d - CHA3_GRP0 - Mesh Credit Configuration + device pci 0a.4 on end # 0x344d - CHA4_GRP0 - Mesh Credit Configuration + device pci 0a.5 on end # 0x344d - CHA5_GRP0 - Mesh Credit Configuration + device pci 1d.0 on end # 0x344f - CHAALL0 - Multicast DRAM Rules + device pci 1d.1 on end # 0x3457 - CHAALL1 - Multicast MMIO Rules + device pci 1e.0 on end # 0x3458 - Power Control Unit (PCU) + device pci 1e.1 on end # 0x3459 - PCU + device pci 1e.2 on end # 0x345a - PCU + device pci 1e.3 on end # 0x345b - PCU + device pci 1e.4 on end # 0x345c - PCU + device pci 1e.5 on end # 0x345d - PCU + device pci 1e.6 on end # 0x345e - PCU + device pci 1e.7 on end # 0x345f - PCU + end # D8 U1 + device domain 9 on # additional root bus 0xE7 for domain/stack 2 + device pci 0.0 on end # 0x270b - Hardware Queue Manager (HQM) + end +end #chip diff --git a/src/mainboard/intel/frost_creek/dsdt.asl b/src/mainboard/intel/frost_creek/dsdt.asl new file mode 100644 index 0000000..82fbb21 --- /dev/null +++ b/src/mainboard/intel/frost_creek/dsdt.asl @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20240225 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + /* SNR ACPI tables */ + #include <soc/intel/snowridge/acpi/uncore.asl> +} diff --git a/src/mainboard/intel/frost_creek/gpio.inc b/src/mainboard/intel/frost_creek/gpio.inc new file mode 100644 index 0000000..4e85a8a --- /dev/null +++ b/src/mainboard/intel/frost_creek/gpio.inc @@ -0,0 +1,221 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MAINBOARD_FROST_CREEK_GPIO_INC_ +#define _MAINBOARD_FROST_CREEK_GPIO_INC_ + +#include <soc/gpio_defs.h> +#include <soc/gpio_snr.h> +#include <intelblocks/gpio.h> +#include <intelblocks/gpio_defs.h> + +struct snr_pad_config frost_creek_gpio_table[] = { + SNR_PAD_CFG_STRUCT0(GPIO_WEST2_4, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, + GPIO_HOSTSW_OWN_DEFAULT), + SNR_PAD_CFG_STRUCT0(GPIO_WEST2_5, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, + GPIO_HOSTSW_OWN_DEFAULT), + SNR_PAD_CFG_STRUCT0(GPIO_WEST2_6, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, + GPIO_HOSTSW_OWN_DEFAULT), + SNR_PAD_CFG_STRUCT0(GPIO_WEST2_7, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, + GPIO_HOSTSW_OWN_DEFAULT), + SNR_PAD_CFG_STRUCT0(GPIO_WEST2_8, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, + GPIO_HOSTSW_OWN_DEFAULT), + SNR_PAD_CFG_STRUCT0(GPIO_WEST2_9, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, + GPIO_HOSTSW_OWN_DEFAULT), + SNR_PAD_CFG_STRUCT0(GPIO_WEST2_10, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, + GPIO_HOSTSW_OWN_DEFAULT), + SNR_PAD_CFG_STRUCT0(GPIO_WEST2_11, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, + GPIO_HOSTSW_OWN_DEFAULT), + SNR_PAD_CFG_STRUCT0(GPIO_WEST2_18, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_WEST2_19, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_WEST2_20, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_WEST01_0, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_WEST01_1, PAD_FUNC(GPIO), PAD_CFG0_MODE_MASK, + GPIO_HOSTSW_OWN_DEFAULT), + SNR_PAD_CFG_STRUCT0(GPIO_WEST01_4, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_WEST01_5, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_WEST01_6, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_WEST01_7, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_WEST01_8, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_WEST01_9, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_WEST01_10, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_WEST01_11, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE), + PAD_CFG0_RXINV_MASK | PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | + PAD_CFG0_TX_DISABLE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_WEST5_15, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE), + PAD_CFG0_RXINV_MASK | PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | + PAD_CFG0_TX_DISABLE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_WEST5_16, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_WEST5_17, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_WEST5_18, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_WESTB_8, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE), + PAD_CFG0_RXINV_MASK | PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | + PAD_CFG0_TX_DISABLE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0( + GPIO_WESTB_11, + PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(SCI) | PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE), + PAD_CFG0_RXINV_MASK | PAD_CFG0_TRIG_MASK | PAD_CFG0_ROUTE_MASK | + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_EAST2_6, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_EAST2_10, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_EAST2_11, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0( + GPIO_EAST2_12, + PAD_TRIG(LEVEL) | PAD_IRQ_ROUTE(IOAPIC) | PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE), + PAD_CFG0_TRIG_MASK | PAD_CFG0_RXINV_MASK | PAD_CFG0_ROUTE_MASK | + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_EAST2_13, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE), + PAD_CFG0_RXINV_MASK | PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | + PAD_CFG0_TX_DISABLE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_EAST2_14, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_EAST2_17, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_EAST2_18, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_EAST2_19, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_EAST2_20, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_EAST2_22, PAD_FUNC(GPIO) | PAD_BUF(TX_DISABLE), + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_EAST2_23, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_EAST0_10, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_EAST0_11, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_EAST0_18, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT0(GPIO_EAST0_19, PAD_FUNC(GPIO), PAD_CFG0_MODE_MASK, + GPIO_HOSTSW_OWN_DEFAULT), + SNR_PAD_CFG_STRUCT0(GPIO_EAST0_21, + PAD_FUNC(GPIO) | PAD_BUF(RX_DISABLE) | PAD_CFG0_TX_STATE, + PAD_CFG0_MODE_MASK | PAD_CFG0_RX_DISABLE | PAD_CFG0_TX_DISABLE | + PAD_CFG0_TX_STATE, + GPIO_HOSTSW_OWN_DRIVER), + SNR_PAD_CFG_STRUCT1(GPIO_EMMC_0, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, PAD_PULL(UP_20K), + PAD_CFG1_PULL_MASK, GPIO_HOSTSW_OWN_DEFAULT), + SNR_PAD_CFG_STRUCT1(GPIO_EMMC_1, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, PAD_PULL(DN_20K), + PAD_CFG1_PULL_MASK, GPIO_HOSTSW_OWN_DEFAULT), + SNR_PAD_CFG_STRUCT1(GPIO_EMMC_2, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, PAD_PULL(UP_20K), + PAD_CFG1_PULL_MASK, GPIO_HOSTSW_OWN_DEFAULT), + SNR_PAD_CFG_STRUCT1(GPIO_EMMC_3, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, PAD_PULL(UP_20K), + PAD_CFG1_PULL_MASK, GPIO_HOSTSW_OWN_DEFAULT), + SNR_PAD_CFG_STRUCT1(GPIO_EMMC_4, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, PAD_PULL(UP_20K), + PAD_CFG1_PULL_MASK, GPIO_HOSTSW_OWN_DEFAULT), + SNR_PAD_CFG_STRUCT1(GPIO_EMMC_5, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, PAD_PULL(UP_20K), + PAD_CFG1_PULL_MASK, GPIO_HOSTSW_OWN_DEFAULT), + SNR_PAD_CFG_STRUCT1(GPIO_EMMC_6, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, PAD_PULL(UP_20K), + PAD_CFG1_PULL_MASK, GPIO_HOSTSW_OWN_DEFAULT), + SNR_PAD_CFG_STRUCT1(GPIO_EMMC_7, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, PAD_PULL(UP_20K), + PAD_CFG1_PULL_MASK, GPIO_HOSTSW_OWN_DEFAULT), + SNR_PAD_CFG_STRUCT1(GPIO_EMMC_8, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, PAD_PULL(UP_20K), + PAD_CFG1_PULL_MASK, GPIO_HOSTSW_OWN_DEFAULT), + SNR_PAD_CFG_STRUCT1(GPIO_EMMC_9, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, PAD_PULL(UP_20K), + PAD_CFG1_PULL_MASK, GPIO_HOSTSW_OWN_DEFAULT), + SNR_PAD_CFG_STRUCT1(GPIO_EMMC_10, PAD_FUNC(NF1), PAD_CFG0_MODE_MASK, PAD_PULL(UP_20K), + PAD_CFG1_PULL_MASK, GPIO_HOSTSW_OWN_DEFAULT)}; + +#endif // _MAINBOARD_FROST_CREEK_GPIO_INC_ diff --git a/src/mainboard/intel/frost_creek/ramstage.c b/src/mainboard/intel/frost_creek/ramstage.c new file mode 100644 index 0000000..fe112fb --- /dev/null +++ b/src/mainboard/intel/frost_creek/ramstage.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <ramstage.h> + +void mainboard_silicon_init_params(FSPS_UPD *supd) +{ + /** + * Default eMMC DLL configuration. + */ + static BL_SCS_SD_DLL frost_creek_emmc_config = {0x00000500, 0x00000910, 0x2a2b292a, + 0x1c1d251c, 0x0001000c, 0x00001818}; + + supd->FspsConfig.PcdEMMCDLLConfigPtr = (UINT32)&frost_creek_emmc_config; + printk(BIOS_DEBUG, "[cb] PcdEMMCDLLConfigPtr: 0x%08x\n", + supd->FspsConfig.PcdEMMCDLLConfigPtr); +} diff --git a/src/mainboard/intel/frost_creek/ramstage.h b/src/mainboard/intel/frost_creek/ramstage.h new file mode 100644 index 0000000..50dc0d6 --- /dev/null +++ b/src/mainboard/intel/frost_creek/ramstage.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MAINBOARD_FROST_CREEK_RAMSTAGE_H_ +#define _MAINBOARD_FROST_CREEK_RAMSTAGE_H_ + +#include <fsp/soc_binding.h> + +void mainboard_silicon_init_params(FSPS_UPD *supd); + +#endif // _MAINBOARD_FROST_CREEK_RAMSTAGE_H_ diff --git a/src/mainboard/intel/frost_creek/romstage.c b/src/mainboard/intel/frost_creek/romstage.c new file mode 100644 index 0000000..4e49a3e --- /dev/null +++ b/src/mainboard/intel/frost_creek/romstage.c @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boardid.h> +#include <commonlib/bsd/helpers.h> +#include <console/console.h> +#include <romstage.h> +#include <soc/gpio_snr.h> /**< For `gpio_configure_snr_pads()`. */ +#include <stddef.h> + +#include "board_id.h" +#include "gpio.inc" + +/* + * Configure GPIO depend on platform + */ +void mainboard_config_gpios(void) +{ + size_t num; + struct snr_pad_config *table; + uint32_t boardid = board_id(); + + /** + * Configure pads prior to FspSiliconInit() in case there's any + * dependencies during hardware initialization. + */ + switch (boardid) { + case BOARD_ID_FROST_CREEK: + table = frost_creek_gpio_table; + num = ARRAY_SIZE(frost_creek_gpio_table); + break; + default: + table = NULL; + num = 0; + break; + } + + if (!table || num == 0) { + printk(BIOS_ERR, "ERROR: No valid GPIO table found!\n"); + return; + } + + printk(BIOS_INFO, "GPIO table: %p, entry num: %zu!\n", table, num); + gpio_configure_snr_pads(table, num); +} + +static void mainboard_hsio_config_params(FSPM_UPD *mupd) +{ + static BL_HSIO_INFORMATION high_speed_io_config; + uint8_t lane; + + for (lane = 0; lane < BL_MAX_FIA_LANES; lane++) { + high_speed_io_config.FiaLaneConfig[lane] = BL_FIA_LANE_OVERRIDE_DISABLED; + high_speed_io_config.FiaLaneLinkWidth[lane] = + BL_FIA_LANE_PCIE_ROOT_PORT_LINK_WIDTH_SET_BY_BICTRL; + } + + mupd->FspmConfig.PcdFiaLaneConfigPtr = (uint32_t)&high_speed_io_config; +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + mainboard_hsio_config_params(mupd); +} diff --git a/src/mainboard/intel/frost_creek/romstage.h b/src/mainboard/intel/frost_creek/romstage.h new file mode 100644 index 0000000..3b4a2ac --- /dev/null +++ b/src/mainboard/intel/frost_creek/romstage.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _MAINBOARD_FROST_CREEK_ROMSTAGE_H_ +#define _MAINBOARD_FROST_CREEK_ROMSTAGE_H_ + +#include <fsp/soc_binding.h> + +void mainboard_config_gpios(void); +void mainboard_memory_init_params(FSPM_UPD *m_upd); + +#endif // _MAINBOARD_FROST_CREEK_ROMSTAGE_H_
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Name of user not set (Code Review)