Change in coreboot[master]: soc/amd/cezanne: Correct S0i3 verstage softfuse bit

[Rob Barnes (Code Review)]

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60214 )

Change subject: soc/amd/cezanne: Correct S0i3 verstage softfuse bit
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soc/amd/cezanne: Correct S0i3 verstage softfuse bit

PSP_S0I3_RESUME_VERSTAGE softfuse bit is 58, not 40.

BUG=b:202397678
BRANCH=None
TEST=Boot guybrush, ensure S0i3 verstage runs with
latest PSP.

Change-Id: Ia27f6e48e345aac0d5f6579d663a6b655688239a
Signed-off-by: Rob Barnes 
---
M src/soc/amd/cezanne/Makefile.inc
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/60214/1

diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc
index a05da8d..050ba44 100644
--- a/src/soc/amd/cezanne/Makefile.inc
+++ b/src/soc/amd/cezanne/Makefile.inc
@@ -111,7 +111,7 @@
 endif

ifeq ($(CONFIG_PSP_S0I3_RESUME_VERSTAGE),y)
-PSP_SOFTFUSE_BITS += 40
+PSP_SOFTFUSE_BITS += 58
 endif

# Use additional Soft Fuse bits specified in Kconfig