Change in ...coreboot[master]: src/southbridge/intel/i82801gx/pcie.c: Correct NULL check

[Jacob Garber (Code Review)]

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31866

Change subject: src/southbridge/intel/i82801gx/pcie.c: Correct NULL check
......................................................................

src/southbridge/intel/i82801gx/pcie.c: Correct NULL check

Check if `pcie_dev` is NULL instead of `dev`. This was flagged
as REVERSE_INULL during a Coverity scan, but is a simple typo.

Signed-off-by: Jacob Garber 
Change-Id: Idc40574b9341d1b10cb2136cbc1a865efa3ab3ee
---
M src/southbridge/intel/i82801gx/pcie.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/31866/1

diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c
index 81679a9..f8bce6a 100644
--- a/src/southbridge/intel/i82801gx/pcie.c
+++ b/src/southbridge/intel/i82801gx/pcie.c
@@ -191,7 +191,7 @@

pcie_dev = rpc.ports[i];

-		if (dev == NULL) {
+		if (pcie_dev == NULL) {
    		printk(BIOS_ERR, "Root Port %d device is NULL?\n", i + 1);
    		continue;
    	}

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31866 )

Change subject: src/southbridge/intel/i82801gx/pcie.c: Correct NULL check
......................................................................

Patch Set 2: Code-Review+1

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31866 )

Change subject: src/southbridge/intel/i82801gx/pcie.c: Correct NULL check
......................................................................

Patch Set 2: Code-Review+2

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31866 )

Change subject: src/southbridge/intel/i82801gx/pcie.c: Correct NULL check
......................................................................

Patch Set 2:

Maybe rebase on master ?

[Jacob Garber (Code Review)]

Jacob Garber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31866 )

Change subject: src/southbridge/intel/i82801gx/pcie.c: Correct NULL check
......................................................................

Patch Set 2:

Hmm, I tried that. I'm not sure what's causing the conflict. Maybe the other patch I submitted? (This one is based off that)

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31866 )

Change subject: src/southbridge/intel/i82801gx/pcie.c: Correct NULL check
......................................................................

Patch Set 2:
> Hmm, I tried that. I'm not sure what's causing the conflict. Maybe
> the other patch I submitted? (This one is based off that)

there is no conflict, this patch required
> Hmm, I tried that. I'm not sure what's causing the conflict. Maybe
> the other patch I submitted? (This one is based off that)

yep.
current patch requires Clang-formating's patch.

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded a new patch set (#3) to the change originally created by Jacob Garber. ( https://review.coreboot.org/c/coreboot/+/31866 )

Change subject: src/southbridge/intel/i82801gx/pcie.c: Correct NULL check
......................................................................

src/southbridge/intel/i82801gx/pcie.c: Correct NULL check

Check if `pcie_dev` is NULL instead of `dev`. This was flagged
as REVERSE_INULL during a Coverity scan, but is a simple typo.

Signed-off-by: Jacob Garber 
Change-Id: Idc40574b9341d1b10cb2136cbc1a865efa3ab3ee
---
M src/southbridge/intel/i82801gx/pcie.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/31866/3

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31866 )

Change subject: src/southbridge/intel/i82801gx/pcie.c: Correct NULL check
......................................................................

Patch Set 3: Code-Review+2

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31866 )

Change subject: src/southbridge/intel/i82801gx/pcie.c: Correct NULL check
......................................................................

src/southbridge/intel/i82801gx/pcie.c: Correct NULL check

Check if `pcie_dev` is NULL instead of `dev`. This was flagged
as REVERSE_INULL during a Coverity scan, but is a simple typo.

Signed-off-by: Jacob Garber 
Change-Id: Idc40574b9341d1b10cb2136cbc1a865efa3ab3ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31866
Reviewed-by: HAOUAS Elyes 
Tested-by: build bot (Jenkins) 
---
M src/southbridge/intel/i82801gx/pcie.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  HAOUAS Elyes: Looks good to me, approved

diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c
index 4679ee5..9446527 100644
--- a/src/southbridge/intel/i82801gx/pcie.c
+++ b/src/southbridge/intel/i82801gx/pcie.c
@@ -195,7 +195,7 @@

pcie_dev = rpc.ports[i];

-		if (dev == NULL) {
+		if (pcie_dev == NULL) {
    		printk(BIOS_ERR, "Root Port %d device is NULL?\n",
    		       i + 1);
    		continue;