Change in coreboot[master]: soc/intel/alderlake: Add EPP override support

[Cliff Huang (Code Review)]

Attention is currently required from: Cliff Huang.
Hello Cliff Huang,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/62654

to review the following change.

Change subject: soc/intel/alderlake: Add EPP override support
......................................................................

soc/intel/alderlake: Add EPP override support

This update energy performance preference value to all logic CPUs.

BUG=b:219785001
BRANCH=firmware
BRANCH=firmware-brya-14505.Bre-brya-14505.B

Signed-off-by: Cliff Huang 
Change-Id: Ie59623fe715b0c545f8d4b6c22ab2ce670a29798
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/cpu.c
2 files changed, 26 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/62654/1

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 6766406..1cca44e 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -564,6 +564,10 @@
     * Default 0. Setting this to 1 enable CNVi DDR RFIM.
     */
    bool CnviDdrRfim;
+
+	/* Energy-Performance Preference (HWP feature) */
+	bool enable_energy_perf_pref;
+	uint8_t energy_perf_pref_value;
 };

typedef struct soc_intel_alderlake_config config_t;
diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index 66db16b..912025b 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -122,6 +122,14 @@
    /* Set energy policy */
    set_energy_perf_bias(ENERGY_POLICY_NORMAL);

+	const config_t *conf = config_of_soc();
+	/* Set energy-performance preference */
+	if (conf->enable_energy_perf_pref) {
+		if (check_energy_perf_cap()) {
+			set_energy_perf_pref(conf->energy_perf_pref_value);
+		} else
+			printk(BIOS_WARNING, "Engery Performance Preference not supported!\n");
+	}
    /* Enable Turbo */
    enable_turbo();
 }
@@ -132,6 +140,19 @@
    smm_relocate();
 }

+static void pre_mp_init(void)
+{
+	soc_fsp_load();
+
+	const config_t *conf = config_of_soc();
+	if (conf->enable_energy_perf_pref) {
+		if (check_energy_perf_cap()) {
+			enable_energy_perf_pref();
+		} else
+			printk(BIOS_WARNING, "Engery Performance Preference not supported!\n");
+    }
+}
+
 static void post_mp_init(void)
 {
    /* Set Max Ratio */
@@ -152,7 +173,7 @@
     * that are set prior to ramstage.
     * Real MTRRs programming are being done after resource allocation.
     */
-	.pre_mp_init = soc_fsp_load,
+	.pre_mp_init = pre_mp_init,
    .get_cpu_count = get_cpu_count,
    .get_smm_info = smm_info,
    .get_microcode_info = get_microcode_info,