Change in coreboot[master]: Revert "soc/amd/cezanne: Start loading APOB asynchronously"

[Raul Rangel (Code Review)]

Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held.
Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59500 )

Change subject: Revert "soc/amd/cezanne: Start loading APOB asynchronously"
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Revert "soc/amd/cezanne: Start loading APOB asynchronously"

This reverts commit 61f44127f0c06688343fdfa3f518a58b4efe170c.

We now support coop-threads in romstage. This means we can use the SPI
DMA controller to preload the APOB while FSP-M executes. This will give
us more time to preload things in ramstage while FSP-S is executing.

BUG=b:179699789
TEST=build guybrush

Signed-off-by: Raul E Rangel 
Change-Id: I8bd19ab1b202322ea6b185a660517d03c700d436
---
M src/soc/amd/cezanne/fsp_s_params.c
1 file changed, 0 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/59500/1

diff --git a/src/soc/amd/cezanne/fsp_s_params.c b/src/soc/amd/cezanne/fsp_s_params.c
index 0aa3c96..64cc722 100644
--- a/src/soc/amd/cezanne/fsp_s_params.c
+++ b/src/soc/amd/cezanne/fsp_s_params.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <acpi/acpi.h>
-#include <amdblocks/apob_cache.h>
 #include <device/pci.h>
 #include <fsp/api.h>
 #include <program_loading.h>
@@ -33,7 +32,6 @@
     * for the FSP-S preload has been freed, so we don't have to worry about exhausting the
     * cbfs_cache.
     */
-	start_apob_cache_read();
    if (!acpi_is_wakeup_s3())
    	payload_preload();
 }