Change in ...coreboot[master]: soc/intel/braswell: Correct configuration of interrupts - coreboot-gerrit

28 Feb 2019


      Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29419 )
Change subject: soc/intel/braswell: Correct configuration of interrupts
......................................................................
Patch Set 5: Code-Review+2
Tested with Intel Celeron 3160 and 3060 by booting Debian or SeaBIOS. SeaBIOS won't run properly without interrupts and configured PIC.
-- 
To view, visit https://review.coreboot.org/c/coreboot/+/29419
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I128cb35dd0e348a9cd9fb162651e0aa2b7e4a3ef
Gerrit-Change-Number: 29419
Gerrit-PatchSet: 5
Gerrit-Owner: Frans Hendriks fhendriks@eltan.com
Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz
Gerrit-Reviewer: Frans Hendriks fhendriks@eltan.com
Gerrit-Reviewer: Hannah Williams hannah.williams@intel.com
Gerrit-Reviewer: Michał Żygowski michal.zygowski@3mdeb.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Comment-Date: Thu, 28 Feb 2019 08:41:36 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment