HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43704 )
Change subject: src: Add include <types.h> ......................................................................
src: Add include <types.h>
BIT(x) needs <types.h>.
Change-Id: I1a7c5e15468b76e29aa32169fd8ca10445c2eff2 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/acpi/device.c M src/drivers/intel/soundwire/soundwire.h M src/include/acpi/acpi_device.h M src/include/device/soundwire.h M src/northbridge/amd/pi/00730F01/northbridge.c M src/soc/amd/common/block/include/amdblocks/gpio_banks.h M src/soc/amd/common/block/include/amdblocks/spi.h M src/soc/amd/common/block/spi/fch_spi_ctrl.c M src/soc/amd/picasso/include/soc/i2c.h M src/soc/amd/stoneyridge/include/soc/i2c.h M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/tigerlake/chip.h M src/soc/mediatek/common/ddp.c M src/soc/mediatek/common/include/soc/spi_common.h M src/soc/mediatek/mt8173/include/soc/dsi.h M src/soc/mediatek/mt8183/ddp.c M src/soc/mediatek/mt8183/dsi.c M src/soc/mediatek/mt8183/include/soc/dsi.h M src/soc/qualcomm/ipq40xx/include/soc/clock.h M src/soc/qualcomm/qcs405/usb.c M src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h M src/soc/qualcomm/sc7180/qupv3_spi.c M src/southbridge/amd/agesa/hudson/hudson.h 23 files changed, 24 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/43704/1
diff --git a/src/acpi/device.c b/src/acpi/device.c index b119abd..07e80f5 100644 --- a/src/acpi/device.c +++ b/src/acpi/device.c @@ -8,6 +8,7 @@ #include <device/device.h> #include <device/path.h> #include <stdlib.h> +#include <types.h> #include <crc_byte.h>
#if CONFIG(GENERIC_GPIO_LIB) diff --git a/src/drivers/intel/soundwire/soundwire.h b/src/drivers/intel/soundwire/soundwire.h index 3e2addf..6ee1fad 100644 --- a/src/drivers/intel/soundwire/soundwire.h +++ b/src/drivers/intel/soundwire/soundwire.h @@ -4,7 +4,7 @@ #define __DRIVERS_INTEL_SOUNDWIRE_H__
#include <device/soundwire.h> -#include <stdint.h> +#include <types.h>
/** * enum intel_soundwire_quirk - Quirks for controller master links. diff --git a/src/include/acpi/acpi_device.h b/src/include/acpi/acpi_device.h index 6287ba1..9903154 100644 --- a/src/include/acpi/acpi_device.h +++ b/src/include/acpi/acpi_device.h @@ -6,6 +6,7 @@ #include <device/i2c.h> #include <stdint.h> #include <spi-generic.h> +#include <types.h>
enum acpi_dp_type { ACPI_DP_TYPE_UNKNOWN, diff --git a/src/include/device/soundwire.h b/src/include/device/soundwire.h index 85e3186..6f966ae 100644 --- a/src/include/device/soundwire.h +++ b/src/include/device/soundwire.h @@ -16,8 +16,7 @@ #ifndef __DEVICE_SOUNDWIRE_H__ #define __DEVICE_SOUNDWIRE_H__
-#include <stdbool.h> -#include <stdint.h> +#include <types.h>
/** * enum soundwire_limits - Limits on number of SoundWire devices in topology. diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 556e6fc..75e1f02 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -6,7 +6,7 @@ #include <acpi/acpi.h> #include <acpi/acpi_ivrs.h> #include <arch/ioapic.h> -#include <stdint.h> +#include <types.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index 7a9638d9..eea7a979 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -3,9 +3,7 @@ #ifndef __AMDBLOCK_GPIO_BANKS_H__ #define __AMDBLOCK_GPIO_BANKS_H__
-#include <stdint.h> -#include <stdbool.h> -#include <stddef.h> +#include <types.h>
struct soc_amd_gpio { uint8_t gpio; diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index d226e0c..eb8c90a 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -3,6 +3,8 @@ #ifndef __AMDBLOCKS_SPI_H__ #define __AMDBLOCKS_SPI_H__
+#include <types.h> + #define SPI_CNTRL0 0x00 #define SPI_BUSY BIT(31)
diff --git a/src/soc/amd/common/block/spi/fch_spi_ctrl.c b/src/soc/amd/common/block/spi/fch_spi_ctrl.c index 13ad0cd..2be3b1a 100644 --- a/src/soc/amd/common/block/spi/fch_spi_ctrl.c +++ b/src/soc/amd/common/block/spi/fch_spi_ctrl.c @@ -9,6 +9,7 @@ #include <device/pci_ops.h> #include <lib.h> #include <timer.h> +#include <types.h>
#define GRANULARITY_TEST_4k 0x0000f000 /* bits 15-12 */ #define WORD_TO_DWORD_UPPER(x) ((x << 16) & 0xffff0000) diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index 20084f0..c1dd6ef 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -3,6 +3,7 @@ #ifndef __PICASSO_I2C_H__ #define __PICASSO_I2C_H__
+#include <types.h> #include <soc/gpio.h>
struct soc_amd_i2c_save { diff --git a/src/soc/amd/stoneyridge/include/soc/i2c.h b/src/soc/amd/stoneyridge/include/soc/i2c.h index 844ff1b..63db7d4 100644 --- a/src/soc/amd/stoneyridge/include/soc/i2c.h +++ b/src/soc/amd/stoneyridge/include/soc/i2c.h @@ -3,6 +3,7 @@ #ifndef __STONEYRIDGE_I2C_H__ #define __STONEYRIDGE_I2C_H__
+#include <types.h> #include <soc/gpio.h>
struct soc_amd_i2c_save { diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 0cebe32..5b703cf 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -9,7 +9,7 @@ #include <intelblocks/fast_spi.h> #include <intelblocks/msr.h> #include <soc/soc_chip.h> -#include <stdint.h> +#include <types.h>
/* * Set PERF_CTL MSR (0x199) P_Req with diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index 59dab58..dcf668e 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -16,7 +16,7 @@ #include <soc/pmc.h> #include <soc/serialio.h> #include <soc/usb.h> -#include <stdint.h> +#include <types.h>
#define MAX_HD_AUDIO_DMIC_LINKS 2 #define MAX_HD_AUDIO_SNDW_LINKS 4 diff --git a/src/soc/mediatek/common/ddp.c b/src/soc/mediatek/common/ddp.c index 17a2849..67e2fbf 100644 --- a/src/soc/mediatek/common/ddp.c +++ b/src/soc/mediatek/common/ddp.c @@ -4,6 +4,7 @@ #include <edid.h> #include <soc/addressmap.h> #include <soc/ddp.h> +#include <types.h>
#define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) diff --git a/src/soc/mediatek/common/include/soc/spi_common.h b/src/soc/mediatek/common/include/soc/spi_common.h index cb86db3..918f3d2 100644 --- a/src/soc/mediatek/common/include/soc/spi_common.h +++ b/src/soc/mediatek/common/include/soc/spi_common.h @@ -5,6 +5,7 @@
#include <soc/gpio_base.h> #include <spi-generic.h> +#include <types.h>
enum { SPI_CFG1_CS_IDLE_SHIFT = 0, diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h index 6becfce..6f9b301 100644 --- a/src/soc/mediatek/mt8173/include/soc/dsi.h +++ b/src/soc/mediatek/mt8173/include/soc/dsi.h @@ -4,6 +4,7 @@ #define _DSI_REG_H_
#include <soc/dsi_common.h> +#include <types.h>
/* DSI features */ #define MTK_DSI_MIPI_RATIO_NUMERATOR 102 diff --git a/src/soc/mediatek/mt8183/ddp.c b/src/soc/mediatek/mt8183/ddp.c index 13918a0..eba3f5e 100644 --- a/src/soc/mediatek/mt8183/ddp.c +++ b/src/soc/mediatek/mt8183/ddp.c @@ -4,6 +4,7 @@ #include <edid.h> #include <soc/addressmap.h> #include <soc/ddp.h> +#include <types.h>
static void disp_config_main_path_connection(void) { diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c index 9f54f49..fa73ddb 100644 --- a/src/soc/mediatek/mt8183/dsi.c +++ b/src/soc/mediatek/mt8183/dsi.c @@ -5,6 +5,7 @@ #include <delay.h> #include <soc/dsi.h> #include <soc/pll.h> +#include <types.h>
void mtk_dsi_configure_mipi_tx(u32 data_rate, u32 lanes) { diff --git a/src/soc/mediatek/mt8183/include/soc/dsi.h b/src/soc/mediatek/mt8183/include/soc/dsi.h index 4535d90..9da79e6 100644 --- a/src/soc/mediatek/mt8183/include/soc/dsi.h +++ b/src/soc/mediatek/mt8183/include/soc/dsi.h @@ -4,6 +4,7 @@ #define SOC_MEDIATEK_MT8183_DSI_H
#include <soc/dsi_common.h> +#include <types.h>
/* DSI features */ #define MTK_DSI_MIPI_RATIO_NUMERATOR 100 diff --git a/src/soc/qualcomm/ipq40xx/include/soc/clock.h b/src/soc/qualcomm/ipq40xx/include/soc/clock.h index 2b48a2c..6859b1f 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/clock.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/clock.h @@ -5,6 +5,7 @@ #define __IPQ40XX_CLOCK_H_
#include <soc/iomap.h> +#include <types.h>
/* UART clock @ 7.3728 MHz */ #define UART_DM_CLK_RX_TX_BIT_RATE 0xFF diff --git a/src/soc/qualcomm/qcs405/usb.c b/src/soc/qualcomm/qcs405/usb.c index 3820e13..738e56f 100644 --- a/src/soc/qualcomm/qcs405/usb.c +++ b/src/soc/qualcomm/qcs405/usb.c @@ -5,6 +5,7 @@ #include <delay.h> #include <soc/usb.h> #include <soc/clock.h> +#include <types.h>
/* USB BASE ADDRESS */ #define USB_HOST0_DWC3_BASE 0x758C100 diff --git a/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h b/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h index 9f5806f..9df5102 100644 --- a/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h +++ b/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h @@ -7,8 +7,8 @@ #include <device/mmio.h> #include <gpio.h> #include <soc/addressmap.h> -#include <stdint.h> #include <timer.h> +#include <types.h>
#define GENMASK(h, l) (BIT(h + 1) - BIT(l))
diff --git a/src/soc/qualcomm/sc7180/qupv3_spi.c b/src/soc/qualcomm/sc7180/qupv3_spi.c index c3827ef..a145417 100644 --- a/src/soc/qualcomm/sc7180/qupv3_spi.c +++ b/src/soc/qualcomm/sc7180/qupv3_spi.c @@ -8,6 +8,7 @@ #include <soc/qcom_qup_se.h> #include <soc/qupv3_config.h> #include <soc/qupv3_spi.h> +#include <types.h>
/* SE_SPI_LOOPBACK register fields */ #define LOOPBACK_ENABLE 0x1 diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 9b6663a..eeb60ca 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -4,6 +4,7 @@ #define HUDSON_H
#include <device/device.h> +#include <types.h>
/* Power management index/data registers */ #define BIOSRAM_INDEX 0xcd4
Hello Angel Pons, Julius Werner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43704
to look at the new patch set (#2).
Change subject: src: Add include <types.h> ......................................................................
src: Add include <types.h>
BIT(x) needs <types.h>.
Change-Id: I1a7c5e15468b76e29aa32169fd8ca10445c2eff2 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/acpi/device.c M src/drivers/intel/soundwire/soundwire.h M src/include/acpi/acpi_device.h M src/include/device/soundwire.h M src/northbridge/amd/pi/00730F01/northbridge.c M src/soc/amd/common/block/include/amdblocks/gpio_banks.h M src/soc/amd/common/block/include/amdblocks/spi.h M src/soc/amd/common/block/spi/fch_spi_ctrl.c M src/soc/amd/picasso/include/soc/i2c.h M src/soc/amd/stoneyridge/include/soc/i2c.h M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/tigerlake/chip.h M src/soc/mediatek/common/ddp.c M src/soc/mediatek/common/include/soc/spi_common.h M src/soc/mediatek/mt8173/include/soc/dsi.h M src/soc/mediatek/mt8183/ddp.c M src/soc/mediatek/mt8183/dsi.c M src/soc/mediatek/mt8183/include/soc/dsi.h M src/soc/qualcomm/ipq40xx/include/soc/clock.h M src/soc/qualcomm/qcs405/usb.c M src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h M src/soc/qualcomm/sc7180/qupv3_spi.c M src/southbridge/amd/agesa/hudson/hudson.h 23 files changed, 24 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/43704/2
Hello Angel Pons, Julius Werner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43704
to look at the new patch set (#3).
Change subject: src: Add include <types.h> ......................................................................
src: Add include <types.h>
BIT(x) needs <types.h>.
Change-Id: I1a7c5e15468b76e29aa32169fd8ca10445c2eff2 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/acpi/device.c M src/drivers/intel/soundwire/soundwire.h M src/include/device/soundwire.h M src/northbridge/amd/pi/00730F01/northbridge.c M src/soc/amd/common/block/include/amdblocks/gpio_banks.h M src/soc/amd/common/block/include/amdblocks/spi.h M src/soc/amd/common/block/spi/fch_spi_ctrl.c M src/soc/amd/picasso/include/soc/i2c.h M src/soc/amd/stoneyridge/include/soc/i2c.h M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/tigerlake/chip.h M src/soc/mediatek/common/ddp.c M src/soc/mediatek/common/include/soc/spi_common.h M src/soc/mediatek/mt8173/include/soc/dsi.h M src/soc/mediatek/mt8183/ddp.c M src/soc/mediatek/mt8183/dsi.c M src/soc/mediatek/mt8183/include/soc/dsi.h M src/soc/qualcomm/ipq40xx/include/soc/clock.h M src/soc/qualcomm/qcs405/usb.c M src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h M src/soc/qualcomm/sc7180/qupv3_spi.c M src/southbridge/amd/agesa/hudson/hudson.h 22 files changed, 23 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/43704/3
Hello Angel Pons, Julius Werner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43704
to look at the new patch set (#4).
Change subject: src: Add include <types.h> ......................................................................
src: Add include <types.h>
BIT(x) needs <types.h>.
Change-Id: I1a7c5e15468b76e29aa32169fd8ca10445c2eff2 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/acpi/device.c M src/drivers/intel/soundwire/soundwire.h M src/northbridge/amd/pi/00730F01/northbridge.c M src/soc/amd/common/block/include/amdblocks/gpio_banks.h M src/soc/amd/common/block/include/amdblocks/spi.h M src/soc/amd/common/block/spi/fch_spi_ctrl.c M src/soc/amd/picasso/include/soc/i2c.h M src/soc/amd/stoneyridge/include/soc/i2c.h M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/tigerlake/chip.h M src/soc/mediatek/common/ddp.c M src/soc/mediatek/common/include/soc/spi_common.h M src/soc/mediatek/mt8173/include/soc/dsi.h M src/soc/mediatek/mt8183/ddp.c M src/soc/mediatek/mt8183/dsi.c M src/soc/mediatek/mt8183/include/soc/dsi.h M src/soc/qualcomm/ipq40xx/include/soc/clock.h M src/soc/qualcomm/qcs405/usb.c M src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h M src/soc/qualcomm/sc7180/qupv3_spi.c M src/southbridge/amd/agesa/hudson/hudson.h 21 files changed, 22 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/43704/4
Hello Angel Pons, Julius Werner, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43704
to look at the new patch set (#5).
Change subject: src/acpi/device.c: Add include <types.h> ......................................................................
src/acpi/device.c: Add include <types.h>
BIT(x) needs <types.h>.
Change-Id: I1a7c5e15468b76e29aa32169fd8ca10445c2eff2 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/acpi/device.c 1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/43704/5
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43704 )
Change subject: src/acpi/device.c: Add include <types.h> ......................................................................
Patch Set 5: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43704 )
Change subject: src/acpi/device.c: Add include <types.h> ......................................................................
src/acpi/device.c: Add include <types.h>
BIT(x) needs <types.h>.
Change-Id: I1a7c5e15468b76e29aa32169fd8ca10445c2eff2 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/43704 Reviewed-by: Angel Pons th3fanbus@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/acpi/device.c 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/src/acpi/device.c b/src/acpi/device.c index b119abd..07e80f5 100644 --- a/src/acpi/device.c +++ b/src/acpi/device.c @@ -8,6 +8,7 @@ #include <device/device.h> #include <device/path.h> #include <stdlib.h> +#include <types.h> #include <crc_byte.h>
#if CONFIG(GENERIC_GPIO_LIB)
-
Angel Pons (Code Review) -
HAOUAS Elyes (Code Review)
-
Patrick Georgi (Code Review)