Change in coreboot[master]: mainboard/volteer: enable early tcss chrome ec related code in mainboard
Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
mainboard/volteer: enable early tcss chrome ec related code in mainboard
Since mainboard is the determining factor if a board uses chrome ec or not moving the early tcss code that relies on chrome ec from soc code to mainboard.
BUG=b:151731851 BRANCH=none TEST=Built and verified that external display is coming up during recovery
Change-Id: I08c151caa84c1970c77386d9eca156fd3c7f2a12 Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com --- M src/mainboard/google/volteer/mainboard.c M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 2 files changed, 76 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/45742/1
diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 23c3e92..80a04d0 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -5,9 +5,11 @@ #include <baseboard/variants.h> #include <device/device.h> #include <drivers/spi/tpm/tpm.h> +#include <ec/google/chromeec/ec.h> #include <ec/ec.h> #include <fw_config.h> #include <security/tpm/tss.h> +#include <soc/early_tcss.h> #include <soc/gpio.h> #include <soc/ramstage.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -65,6 +67,78 @@ } }
+void mainboard_early_tcss_enable(void) +{ + uint8_t dp_mode; + unsigned int num_ports; + int ret, i; + bool ufp, acc; + + ret = google_chromeec_get_num_pd_ports(&num_ports); + if (ret < 0) { + printk(BIOS_ERR, "get_num_pd_ports failed unable to continue\n"); + return; + } + + for (i = 0; i < num_ports; i++) { + uint8_t port_map, mux_flags; + struct tcss_mux mux_data; + + ret = google_chromeec_usb_get_pd_mux_info(i, &mux_flags); + if (ret < 0) { + printk(BIOS_ERR, "port C%d: get_pd_mux_info failed\n", i); + continue; + } + + ret = google_chromeec_pd_get_port_info(i, &port_map); + if (ret < 0) { + printk(BIOS_ERR, "port C%d: get_port_info failed\n", i); + continue; + } + + mux_data.usb2_port = port_map & USB_2_PORT_MASK; + mux_data.usb3_port = (port_map & USB_3_PORT_MASK) >> 4; + + //Add check for connected maybe? + + ret = google_chromeec_usb_pd_control(i, &ufp, &acc, &dp_mode); + if (ret < 0) { + printk(BIOS_ERR, "port C%d: pd_control failed\n", i); + continue; + } + + mux_data.usb = !!(mux_flags & USB_PD_MUX_USB_ENABLED); + mux_data.dp = !!(mux_flags & USB_PD_MUX_DP_ENABLED); + mux_data.cable = !!(mux_flags & USB_PD_CTRL_ACTIVE_CABLE); + mux_data.polarity = !!(mux_flags & USB_PD_MUX_POLARITY_INVERTED); + mux_data.hpd_irq = !!(mux_flags & USB_PD_MUX_HPD_IRQ); + mux_data.hpd_lvl = !!(mux_flags & USB_PD_MUX_HPD_LVL); + mux_data.ufp = !!ufp; + mux_data.acc = !!acc; + mux_data.dp_mode = dp_mode; + + printk(BIOS_DEBUG, "Port %d mux=0x%x\n" + "USB2 port = %x\n" + "USB3 port = %x\n" + "DP Mode = %x\n" + "dp = %d\n" + "usb = %d\n" + "cable = %d\n" + "polarity = %d\n" + "hpd_lvl = %d\n" + "hpd_irq = %d\n" + "ufp = %d\n" + "dbg_acc = %d\n", + i, (unsigned int)mux_flags, mux_data.usb2_port, + mux_data.usb3_port, mux_data.dp_mode, mux_data.dp, + mux_data.usb, mux_data.cable, mux_data.polarity, + mux_data.hpd_lvl, mux_data.hpd_irq, mux_data.ufp, + mux_data.acc); + + update_tcss_mux(i, mux_data); + } +} + static void mainboard_chip_init(void *chip_info) { const struct pad_config *base_pads; diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 43ba255..179aeb0 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -59,6 +59,8 @@ register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "0"
+ register "RMT" = "1" + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45742/1/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/45742/1/src/mainboard/google/voltee... PS1, Line 62: register "RMT" = "1" Not for this patch
Hello build bot (Jenkins), Martin Roth, Patrick Georgi, Wonkyu Kim, Caveh Jalali, Ravishankar Sarawadi, Duncan Laurie, Tim Wawrzynczak, Srinidhi N Kaushik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45742
to look at the new patch set (#2).
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
mainboard/volteer: enable early tcss chrome ec related code in mainboard
Since mainboard is the determining factor if a board uses chrome ec or not moving the early tcss code that relies on chrome ec from soc code to mainboard.
BUG=b:151731851 BRANCH=none TEST=Built and verified that external display is coming up during recovery
Change-Id: I08c151caa84c1970c77386d9eca156fd3c7f2a12 Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com --- M src/mainboard/google/volteer/mainboard.c 1 file changed, 74 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/45742/2
Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45742/1/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/45742/1/src/mainboard/google/voltee... PS1, Line 62: register "RMT" = "1"
Not for this patch
Done
Hello build bot (Jenkins), Martin Roth, Patrick Georgi, Wonkyu Kim, Caveh Jalali, Ravishankar Sarawadi, Duncan Laurie, Tim Wawrzynczak, Srinidhi N Kaushik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45742
to look at the new patch set (#3).
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
mainboard/volteer: enable early tcss chrome ec related code in mainboard
Since mainboard is the determining factor if a board uses chrome ec or not moving the early tcss code that relies on chrome ec from soc code to mainboard.
BUG=b:151731851 BRANCH=none TEST=Built and verified that external display is coming up during recovery
Change-Id: I08c151caa84c1970c77386d9eca156fd3c7f2a12 Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com --- M src/mainboard/google/volteer/mainboard.c 1 file changed, 72 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/45742/3
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45742/4/src/mainboard/google/voltee... File src/mainboard/google/volteer/mainboard.c:
https://review.coreboot.org/c/coreboot/+/45742/4/src/mainboard/google/voltee... PS4, Line 93: //Hard coding these values until the dynamic setting is upstreamed : if (i == 0) { : mux_data.usb2_port = 9; : mux_data.usb3_port = 1; : } else if (i == 1) { : mux_data.usb2_port = 4; : mux_data.usb3_port = 2; : } CB:44039 is now upstream and CB:45878 is close. This info can be obtained from the devicetree, with just a few small additions after rebasing on 45878 or later (my suggestions here): 1) I would add a `DEVTREE_CONST struct device *pd_muxes[4]" to `struct soc_intel_tigerlake_config`. 2) In volteer's mainboard devicetree, add the alias and the reference: ``` chip soc/intel/tigerlake use conn0 as pd_mux[0] use conn1 as pd_mux[1] ``` 3) Then get a ref to the SoC config here, and get the info from `pd_mux[i]->chip_info`
Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45742/4/src/mainboard/google/voltee... File src/mainboard/google/volteer/mainboard.c:
https://review.coreboot.org/c/coreboot/+/45742/4/src/mainboard/google/voltee... PS4, Line 93: //Hard coding these values until the dynamic setting is upstreamed : if (i == 0) { : mux_data.usb2_port = 9; : mux_data.usb3_port = 1; : } else if (i == 1) { : mux_data.usb2_port = 4; : mux_data.usb3_port = 2; : }
CB:44039 is now upstream and CB:45878 is close. […]
I'll work on that change...want to focus on getting the other 3 patches merged asap so I should have this one update in the next day or so
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45742/4/src/mainboard/google/voltee... File src/mainboard/google/volteer/mainboard.c:
https://review.coreboot.org/c/coreboot/+/45742/4/src/mainboard/google/voltee... PS4, Line 93: //Hard coding these values until the dynamic setting is upstreamed : if (i == 0) { : mux_data.usb2_port = 9; : mux_data.usb3_port = 1; : } else if (i == 1) { : mux_data.usb2_port = 4; : mux_data.usb3_port = 2; : }
I'll work on that change... […]
SG, thanks!
Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45742/4/src/mainboard/google/voltee... File src/mainboard/google/volteer/mainboard.c:
https://review.coreboot.org/c/coreboot/+/45742/4/src/mainboard/google/voltee... PS4, Line 93: //Hard coding these values until the dynamic setting is upstreamed : if (i == 0) { : mux_data.usb2_port = 9; : mux_data.usb3_port = 1; : } else if (i == 1) { : mux_data.usb2_port = 4; : mux_data.usb3_port = 2; : }
SG, thanks!
Running into some build issues with the 45878 patch (conn1 already exists then syntax errors if I just plain remove that) Once I get that sorted I should have an update to this patch
Hello build bot (Jenkins), Furquan Shaikh, Martin Roth, Patrick Georgi, Wonkyu Kim, Caveh Jalali, Ravishankar Sarawadi, Duncan Laurie, Tim Wawrzynczak, Srinidhi N Kaushik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45742
to look at the new patch set (#5).
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
mainboard/volteer: enable early tcss chrome ec related code in mainboard
Since mainboard is the determining factor if a board uses chrome ec or not moving the early tcss code that relies on chrome ec from soc code to mainboard.
BUG=b:151731851 BRANCH=none TEST=Built and verified that external display is coming up during recovery
Change-Id: I08c151caa84c1970c77386d9eca156fd3c7f2a12 Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/mainboard.c 2 files changed, 73 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/45742/5
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45742/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/mainboard.c:
https://review.coreboot.org/c/coreboot/+/45742/5/src/mainboard/google/voltee... PS5, Line 93: //Hard coding these values until the dynamic setting is upstreamed : if (i == 0) { : mux_data.usb2_port = 9; : mux_data.usb3_port = 1; : } else if (i == 1) { : mux_data.usb2_port = 4; : mux_data.usb3_port = 2; : } : Here's what I've got right now: ``` diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index dc6cbf9f4be0..9b6cde2ab2ec 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -6,6 +6,7 @@ #include <device/device.h> #include <drivers/spi/tpm/tpm.h> #include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/chip.h> #include <ec/ec.h> #include <fw_config.h> #include <security/tpm/tss.h> @@ -118,6 +119,33 @@ void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg) } }
+static const struct drivers_intel_pmc_mux_conn_config *get_connector_config(int port) +{ + const struct drivers_intel_pmc_mux_conn_config *config; + const struct ec_google_chromeec_config *ec_config; + const struct device *ec; + + config = NULL; + + /* Find the Chrome EC */ + ec = dev_find_slot_pnp(0x0c, 0x09); + if (!ec) + return NULL; + + ec_config = ec->chip_info; + if (!ec_config) + return NULL; + + if (port >= 0 && port < MAX_TYPEC_PORTS) { + const struct device *conn = ec_config->mux_conn[port]; + if (conn) + config = (const struct drivers_intel_pmc_mux_conn_config *) + conn->chip_info; + } + + return config; +} + void mainboard_early_tcss_enable(void) { uint8_t dp_mode; @@ -134,6 +162,7 @@ void mainboard_early_tcss_enable(void) for (i = 0; i < num_ports; i++) { uint8_t mux_flags; struct tcss_mux mux_data; + const struct drivers_intel_pmc_mux_conn_config *config;
ret = google_chromeec_usb_get_pd_mux_info(i, &mux_flags); if (ret < 0) { @@ -141,21 +170,18 @@ void mainboard_early_tcss_enable(void) continue; }
- //Hard coding these values until the dynamic setting is upstreamed - if (i == 0) { - mux_data.usb2_port = 9; - mux_data.usb3_port = 1; - } else if (i == 1) { - mux_data.usb2_port = 4; - } - ret = google_chromeec_usb_pd_control(i, &ufp, &acc, &dp_mode); if (ret < 0) { printk(BIOS_ERR, "port C%d: pd_control failed\n", i); continue; }
+ config = get_connector_config(i); + if (config) { + mux_data.usb2_port = config->usb2_port_number; + mux_data.usb3_port = config->usb3_port_number; + } + mux_data.usb = !!(mux_flags & USB_PD_MUX_USB_ENABLED); mux_data.dp = !!(mux_flags & USB_PD_MUX_DP_ENABLED); mux_data.cable = !!(mux_flags & USB_PD_CTRL_ACTIVE_CABLE);
```
Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45742/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/mainboard.c:
https://review.coreboot.org/c/coreboot/+/45742/5/src/mainboard/google/voltee... PS5, Line 93: //Hard coding these values until the dynamic setting is upstreamed : if (i == 0) { : mux_data.usb2_port = 9; : mux_data.usb3_port = 1; : } else if (i == 1) { : mux_data.usb2_port = 4; : mux_data.usb3_port = 2; : } :
Here's what I've got right now: […]
Ahh I didn't try using the EC devices I added new aliases under SOC to test and thats where I was getting the invalid values for the port numbers back. Will implement using the EC devices and see what the difference is in the return values
Hello build bot (Jenkins), Furquan Shaikh, Martin Roth, Patrick Georgi, Wonkyu Kim, Caveh Jalali, Ravishankar Sarawadi, Duncan Laurie, Tim Wawrzynczak, Srinidhi N Kaushik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45742
to look at the new patch set (#6).
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
mainboard/volteer: enable early tcss chrome ec related code in mainboard
Since mainboard is the determining factor if a board uses chrome ec or not moving the early tcss code that relies on chrome ec from soc code to mainboard.
BUG=b:151731851 BRANCH=none TEST=Built and verified that external display is coming up during recovery
Change-Id: I08c151caa84c1970c77386d9eca156fd3c7f2a12 Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/mainboard.c 2 files changed, 100 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/45742/6
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45742/6/src/mainboard/google/voltee... File src/mainboard/google/volteer/mainboard.c:
https://review.coreboot.org/c/coreboot/+/45742/6/src/mainboard/google/voltee... PS6, Line 133: static const struct drivers_intel_pmc_mux_conn_config *get_connector_config(int port, int num_ports) line over 96 characters
Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45742/5/src/mainboard/google/voltee... File src/mainboard/google/volteer/mainboard.c:
https://review.coreboot.org/c/coreboot/+/45742/5/src/mainboard/google/voltee... PS5, Line 93: //Hard coding these values until the dynamic setting is upstreamed : if (i == 0) { : mux_data.usb2_port = 9; : mux_data.usb3_port = 1; : } else if (i == 1) { : mux_data.usb2_port = 4; : mux_data.usb3_port = 2; : } :
Ahh I didn't try using the EC devices I added new aliases under SOC to test and thats where I was ge […]
Done
Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45742/4/src/mainboard/google/voltee... File src/mainboard/google/volteer/mainboard.c:
https://review.coreboot.org/c/coreboot/+/45742/4/src/mainboard/google/voltee... PS4, Line 93: //Hard coding these values until the dynamic setting is upstreamed : if (i == 0) { : mux_data.usb2_port = 9; : mux_data.usb3_port = 1; : } else if (i == 1) { : mux_data.usb2_port = 4; : mux_data.usb3_port = 2; : }
Running into some build issues with the 45878 patch (conn1 already exists then syntax errors if I ju […]
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
Patch Set 6: Code-Review+1
(4 comments)
https://review.coreboot.org/c/coreboot/+/45742/6/src/mainboard/google/voltee... File src/mainboard/google/volteer/mainboard.c:
https://review.coreboot.org/c/coreboot/+/45742/6/src/mainboard/google/voltee... PS6, Line 164: ret If you use my suggestions below, then `ret` can be deleted as well.
https://review.coreboot.org/c/coreboot/+/45742/6/src/mainboard/google/voltee... PS6, Line 167: ret = google_chromeec_get_num_pd_ports(&num_ports); : if (ret < 0) { : printk(BIOS_ERR, "get_num_pd_ports failed unable to continue\n"); : return; : } ``` if (google_chromeec_get_num_pd_ports(&num_ports) < 0) { printk(BIOS_ERR, "get_num_pd_ports failed unable to continue\n"); return; } ```
? ret isn't used anywhere else
https://review.coreboot.org/c/coreboot/+/45742/6/src/mainboard/google/voltee... PS6, Line 177: : ret = google_chromeec_usb_get_pd_mux_info(i, &mux_flags); : if (ret < 0) { : printk(BIOS_ERR, "port C%d: get_pd_mux_info failed\n", i); : continue; : } ``` if (google_chromeec_usb_get_pd_mux_info(i, &mux_flags) < 0) { printk(BIOS_ERR, "port C%d: get_pd_mux_info failed\n", i); continue; } ```
? ret isn't used anywhere else
https://review.coreboot.org/c/coreboot/+/45742/6/src/mainboard/google/voltee... PS6, Line 184: ret = google_chromeec_usb_pd_control(i, &ufp, &acc, &dp_mode); : if (ret < 0) { : printk(BIOS_ERR, "port C%d: pd_control failed\n", i); : continue; : } ``` if (google_chromeec_usb_pd_control(i, &ufp, &acc, &dp_mode) < 0) { printk(BIOS_ERR, "port C%d: pd_control failed\n", i); continue; } ``` ? ret isn't used anywhere else
Hello build bot (Jenkins), Furquan Shaikh, Martin Roth, Patrick Georgi, Wonkyu Kim, Caveh Jalali, Ravishankar Sarawadi, Tim Wawrzynczak, Duncan Laurie, Tim Wawrzynczak, Srinidhi N Kaushik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45742
to look at the new patch set (#7).
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
mainboard/volteer: enable early tcss chrome ec related code in mainboard
Since mainboard is the determining factor if a board uses chrome ec or not moving the early tcss code that relies on chrome ec from soc code to mainboard.
BUG=b:151731851 BRANCH=none TEST=Built and verified that external display is coming up during recovery
Change-Id: I08c151caa84c1970c77386d9eca156fd3c7f2a12 Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/mainboard.c 2 files changed, 98 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/45742/7
Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
Patch Set 7:
(4 comments)
https://review.coreboot.org/c/coreboot/+/45742/6/src/mainboard/google/voltee... File src/mainboard/google/volteer/mainboard.c:
https://review.coreboot.org/c/coreboot/+/45742/6/src/mainboard/google/voltee... PS6, Line 164: ret
If you use my suggestions below, then `ret` can be deleted as well.
Done
https://review.coreboot.org/c/coreboot/+/45742/6/src/mainboard/google/voltee... PS6, Line 167: ret = google_chromeec_get_num_pd_ports(&num_ports); : if (ret < 0) { : printk(BIOS_ERR, "get_num_pd_ports failed unable to continue\n"); : return; : }
Done
https://review.coreboot.org/c/coreboot/+/45742/6/src/mainboard/google/voltee... PS6, Line 177: : ret = google_chromeec_usb_get_pd_mux_info(i, &mux_flags); : if (ret < 0) { : printk(BIOS_ERR, "port C%d: get_pd_mux_info failed\n", i); : continue; : }
Done
https://review.coreboot.org/c/coreboot/+/45742/6/src/mainboard/google/voltee... PS6, Line 184: ret = google_chromeec_usb_pd_control(i, &ufp, &acc, &dp_mode); : if (ret < 0) { : printk(BIOS_ERR, "port C%d: pd_control failed\n", i); : continue; : }
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45742/7/src/mainboard/google/voltee... File src/mainboard/google/volteer/Kconfig:
https://review.coreboot.org/c/coreboot/+/45742/7/src/mainboard/google/voltee... PS7, Line 18: EARLY_TCSS I don't think we should enable this for volteer right away. It will be required only for those variants that use external display over Type-C. It is good for testing stuff right now, but I think the PMC Mux configuration can wait until depthcharge for variants with internal display.
Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45742/7/src/mainboard/google/voltee... File src/mainboard/google/volteer/Kconfig:
https://review.coreboot.org/c/coreboot/+/45742/7/src/mainboard/google/voltee... PS7, Line 18: EARLY_TCSS
I don't think we should enable this for volteer right away. […]
This patch is being marked a blocker for Delbin as there is a requirement for Type-C external monitor in recovery and during boot. We need to figure out what the clear message will be on this as Duncan has said this is needed.
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45742/7/src/mainboard/google/voltee... File src/mainboard/google/volteer/Kconfig:
https://review.coreboot.org/c/coreboot/+/45742/7/src/mainboard/google/voltee... PS7, Line 18: EARLY_TCSS
This patch is being marked a blocker for Delbin as there is a requirement for Type-C external monito […]
Can you please point me to the bug?
Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45742/7/src/mainboard/google/voltee... File src/mainboard/google/volteer/Kconfig:
https://review.coreboot.org/c/coreboot/+/45742/7/src/mainboard/google/voltee... PS7, Line 18: EARLY_TCSS
Can you please point me to the bug?
The bug this is associated with in the commit message is marked as a blocker for all TCSS/USB4
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45742/7/src/mainboard/google/voltee... File src/mainboard/google/volteer/Kconfig:
https://review.coreboot.org/c/coreboot/+/45742/7/src/mainboard/google/voltee... PS7, Line 18: EARLY_TCSS
The bug this is associated with in the commit message is marked as a blocker for all TCSS/USB4
Posted a comment on the bug and removed the blocker tag.
Hello build bot (Jenkins), Furquan Shaikh, Martin Roth, Patrick Georgi, Wonkyu Kim, Caveh Jalali, Ravishankar Sarawadi, Tim Wawrzynczak, Duncan Laurie, Tim Wawrzynczak, Srinidhi N Kaushik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45742
to look at the new patch set (#8).
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
mainboard/volteer: enable early tcss chrome ec related code in mainboard
Since mainboard is the determining factor if a board uses chrome ec or not moving the early tcss code that relies on chrome ec from soc code to mainboard.
BUG=b:151731851 BRANCH=none TEST=Built and verified that external display is coming up during recovery
Change-Id: I08c151caa84c1970c77386d9eca156fd3c7f2a12 Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/mainboard.c 2 files changed, 98 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/45742/8
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/45742/8/src/mainboard/google/voltee... File src/mainboard/google/volteer/Kconfig:
PS8: I believe this also requires RUN_FSP_GOP, which we do actually define, but we have it in our config.volteer file which gets merged with this config in our build system. I think we'll have to move that config option here so this will compile.
https://review.coreboot.org/c/coreboot/+/45742/8/src/mainboard/google/voltee... PS8, Line 18: select EARLY_TCSS_DISPLAY select EARLY_TCSS_DISPLAY if RUN_FSP_GOP
Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45742/8/src/mainboard/google/voltee... File src/mainboard/google/volteer/Kconfig:
PS8:
I believe this also requires RUN_FSP_GOP, which we do actually define, but we have it in our config. […]
I'll try it out...seems to compile on my system fine with this change but I might have also added RUN_FSP_GOP...Since this is now technically just for debug I'll update it but I don't think this needs to be merged since Volteer variants all have an internal display
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45742 )
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45742/8/src/mainboard/google/voltee... File src/mainboard/google/volteer/Kconfig:
PS8:
I'll try it out... […]
It compiles fine in the chroot (emerge-volteer coreboot) because we have RUN_FSP_GOP=y in third_party/chromiumos-overlay/sys-boot/coreboot/files/configs/config.${board} for all the volteer boards. That file gets merged with the .config from coreboot
Hello build bot (Jenkins), Furquan Shaikh, Martin Roth, Patrick Georgi, Wonkyu Kim, Caveh Jalali, Ravishankar Sarawadi, Tim Wawrzynczak, Duncan Laurie, Tim Wawrzynczak, Srinidhi N Kaushik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/45742
to look at the new patch set (#9).
Change subject: mainboard/volteer: enable early tcss chrome ec related code in mainboard ......................................................................
mainboard/volteer: enable early tcss chrome ec related code in mainboard
Since mainboard is the determining factor if a board uses chrome ec or not moving the early tcss code that relies on chrome ec from soc code to mainboard. This is a sample implementation ass erly display is not required on platforms with internal displays.
BRANCH=none TEST=Built and verified that external display is coming up during recovery
Change-Id: I08c151caa84c1970c77386d9eca156fd3c7f2a12 Signed-off-by: Brandon Breitenstein brandon.breitenstein@intel.com --- M src/mainboard/google/volteer/Kconfig M src/mainboard/google/volteer/mainboard.c 2 files changed, 98 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/45742/9
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Brandon Breitenstein (Code Review) -
build bot (Jenkins) (Code Review)
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Furquan Shaikh (Code Review)
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Tim Wawrzynczak (Code Review)