Attention is currently required from: Lance Zhao, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Julius Werner. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59504 )
Change subject: acpi,Makefile: Add preload_acpi_dsdt ......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
How much is going on in ELOG or APOB? Does the prefetch use case require a buffer for writes to flas […]
Unfortunately the AMD SPI DMA controller is pretty limited. It can only perform reads. Writes requires using command mode API which can only handle 63 bytes per transaction. With the way it's currently implemented, there is a spi_mutex that the SPI DMA controller will grab when performing a transaction. The SPI RW driver will also grab the SPI mutex for ever 63 byte transaction. https://review.coreboot.org/c/coreboot/+/58926
The contention happens if a SPI DMA transaction gets enqueued while writing to the SPI rom. The write will have to wait for the DMA transaction to finish before being started. After the 63 byte write transaction finishes, it's possible for another SPI DMA transaction to be enqueued. Unfortunately the SPI RW code only locks the bus for every 63 byte transaction, not for the whole write. I thought about changing it but it seemed like a lot of risky work.
We could in theory make the ELOG/APOB writes happen in a different thread so that it doesn't matter how long they take. This introduces more complexity though, and honestly I just want to finish working on this so I can move on :)
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Raul Rangel (Code Review)