Change in coreboot[master]: cpu/intel/haswell: Don't change the voltage regulator slow ramp rate

[Tristan Corrick (Code Review)]

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/29384

Change subject: cpu/intel/haswell: Don't change the voltage regulator slow ramp rate
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cpu/intel/haswell: Don't change the voltage regulator slow ramp rate

On my system (Pentium G3258, ASRock H81M-HDS), changing the the slow
ramp rate during `initialize_vr_config()` results in the following
exception, causing the system to hang.

CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7f7a3736 - Halting
    Code: 0 eflags: 00010006 cr2: 00000000
    eax: 00262626 ebx: 00140000 ecx: 00000603 edx: 00360000
    edi: 00000007 esi: 00262626 ebp: 7f7c0fd8 esp: 7f7c0e90

The exception occurs when `MSR_VR_MISC_CONFIG`, located at 0x603, is
written to. This MSR doesn't seem to be documented publicly (except by
this code).

The slow ramp rate is changed by clearing bit 54 and setting bit
53 of the MSR. However, in 16cbf8983c ("haswell: VR controller
configuration"), the MSR on the test system has bit 54 cleared and bit
53 set by default, meaning that explicitly changing is it not necessary.
This is also the default MSR value on an Acer C720 (Google Peppy). On
my Pentium G3258 system, both bit 53 and bit 54 are not set by default,
and keeping it that way prevents the system from hanging. No noticeable
issues arise by having these bits unset. So, leaving the slow ramp rate
at its default should result in the optimal outcome.

Change-Id: I79b10139295741d298ac6c77c4f7272ac151ad90
Signed-off-by: Tristan Corrick 
---
M src/cpu/intel/haswell/haswell_init.c
1 file changed, 0 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/29384/1

diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index c67ef14..fac9e54 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -333,9 +333,6 @@
    msr.hi &= ~(1 << (51 - 32));
    /* Enable decay mode on C-state entry. */
    msr.hi |= (1 << (52 - 32));
-	/* Set the slow ramp rate to be fast ramp rate / 4 */
-	msr.hi &= ~(0x3 << (53 - 32));
-	msr.hi |= (0x01 << (53 - 32));
    /* Set MIN_VID (31:24) to allow CPU to have full control. */
    msr.lo &= ~0xff000000;
    wrmsr(MSR_VR_MISC_CONFIG, msr);