Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43124 )
Change subject: haswell: Automatically determine system type ......................................................................
haswell: Automatically determine system type
Check the PCH's LPC device ID to know the system type instead of relying on hardcoded numbers. The `get_pch_platform_type` function is MRC-safe.
Change-Id: Icfe7c2dccb7c7a178892ad3a2e34ca93b33b2bb9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asrock/b85m_pro4/romstage.c M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/google/beltino/romstage.c M src/mainboard/google/slippy/romstage.c M src/mainboard/intel/baskingridge/romstage.c M src/mainboard/lenovo/t440p/romstage.c M src/mainboard/supermicro/x10slm-f/romstage.c M src/northbridge/intel/haswell/romstage.c 8 files changed, 1 insertion(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/43124/1
diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index a2b8607..f625824 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -18,7 +18,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->system_type = 1; /* Desktop/Server */ pei_data->spd_addresses[0] = 0xa0; pei_data->spd_addresses[1] = 0xa2; pei_data->spd_addresses[2] = 0xa4; diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 761e9d8..cfefdda 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -18,7 +18,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->system_type = 1; /* Desktop/Server */ pei_data->spd_addresses[0] = 0xa0; pei_data->spd_addresses[2] = 0xa4; pei_data->ec_present = 0; diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 8b3ace2..839cd6c 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -41,7 +41,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->system_type = 5; /* ULT */ pei_data->spd_addresses[0] = 0xa0; pei_data->spd_addresses[2] = 0xa4; pei_data->ec_present = 0; diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index bed81c0..e571944 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -42,7 +42,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->system_type = 5; /* ULT */ pei_data->spd_addresses[0] = 0xff; pei_data->spd_addresses[2] = 0xff; pei_data->ec_present = 1; diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 6b7026a..73fc54e 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -42,7 +42,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->system_type = 0; /* 0 Mobile, 1 Desktop/Server */ pei_data->spd_addresses[0] = 0xa0; pei_data->spd_addresses[1] = 0xa2; pei_data->spd_addresses[2] = 0xa4; diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index d716043..9ce4486 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -42,7 +42,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->system_type = 0; /* Mobile */ pei_data->spd_addresses[0] = 0xa0; pei_data->spd_addresses[2] = 0xa2; pei_data->ec_present = 1; diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index ddef657..26f820a 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -18,7 +18,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->system_type = 1; /* Desktop/Server */ pei_data->spd_addresses[0] = 0xa0; pei_data->spd_addresses[1] = 0xa2; pei_data->spd_addresses[2] = 0xa4; diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index f4128b3..57041e0 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -51,6 +51,7 @@ .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .temp_mmio_base = 0xfed08000, + .system_type = get_pch_platform_type(), .tseg_size = CONFIG_SMM_TSEG_SIZE, .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH), .max_ddr3_freq = 1600,
Hello build bot (Jenkins), Tristan Corrick, Alexander Couzens, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43124
to look at the new patch set (#2).
Change subject: haswell: Automatically determine system type ......................................................................
haswell: Automatically determine system type
Check the PCH's LPC device ID to know the system type instead of relying on hardcoded numbers. The `get_pch_platform_type` function is MRC-safe.
Change-Id: Icfe7c2dccb7c7a178892ad3a2e34ca93b33b2bb9 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/asrock/b85m_pro4/romstage.c M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/google/beltino/romstage.c M src/mainboard/google/slippy/romstage.c M src/mainboard/intel/baskingridge/romstage.c M src/mainboard/lenovo/t440p/romstage.c M src/mainboard/supermicro/x10slm-f/romstage.c M src/northbridge/intel/haswell/romstage.c 8 files changed, 1 insertion(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/43124/2
Tristan Corrick has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43124 )
Change subject: haswell: Automatically determine system type ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43124 )
Change subject: haswell: Automatically determine system type ......................................................................
haswell: Automatically determine system type
Check the PCH's LPC device ID to know the system type instead of relying on hardcoded numbers. The `get_pch_platform_type` function is MRC-safe.
Change-Id: Icfe7c2dccb7c7a178892ad3a2e34ca93b33b2bb9 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43124 Reviewed-by: Tristan Corrick tristan@corrick.kiwi Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/asrock/b85m_pro4/romstage.c M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/google/beltino/romstage.c M src/mainboard/google/slippy/romstage.c M src/mainboard/intel/baskingridge/romstage.c M src/mainboard/lenovo/t440p/romstage.c M src/mainboard/supermicro/x10slm-f/romstage.c M src/northbridge/intel/haswell/romstage.c 8 files changed, 1 insertion(+), 7 deletions(-)
Approvals: build bot (Jenkins): Verified Tristan Corrick: Looks good to me, approved
diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index a2b8607..f625824 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -18,7 +18,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->system_type = 1; /* Desktop/Server */ pei_data->spd_addresses[0] = 0xa0; pei_data->spd_addresses[1] = 0xa2; pei_data->spd_addresses[2] = 0xa4; diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 761e9d8..cfefdda 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -18,7 +18,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->system_type = 1; /* Desktop/Server */ pei_data->spd_addresses[0] = 0xa0; pei_data->spd_addresses[2] = 0xa4; pei_data->ec_present = 0; diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 8b3ace2..839cd6c 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -41,7 +41,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->system_type = 5; /* ULT */ pei_data->spd_addresses[0] = 0xa0; pei_data->spd_addresses[2] = 0xa4; pei_data->ec_present = 0; diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index bed81c0..e571944 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -42,7 +42,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->system_type = 5; /* ULT */ pei_data->spd_addresses[0] = 0xff; pei_data->spd_addresses[2] = 0xff; pei_data->ec_present = 1; diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 6b7026a..73fc54e 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -42,7 +42,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->system_type = 0; /* 0 Mobile, 1 Desktop/Server */ pei_data->spd_addresses[0] = 0xa0; pei_data->spd_addresses[1] = 0xa2; pei_data->spd_addresses[2] = 0xa4; diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index 5a5f2de..3678760 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -42,7 +42,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->system_type = 0; /* Mobile */ pei_data->spd_addresses[0] = 0xa0; pei_data->spd_addresses[2] = 0xa2; pei_data->ec_present = 1; diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index ddef657..26f820a 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -18,7 +18,6 @@
void mainboard_fill_pei_data(struct pei_data *pei_data) { - pei_data->system_type = 1; /* Desktop/Server */ pei_data->spd_addresses[0] = 0xa0; pei_data->spd_addresses[1] = 0xa2; pei_data->spd_addresses[2] = 0xa4; diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 42a2a56..40b7b87 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -51,6 +51,7 @@ .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .temp_mmio_base = 0xfed08000, + .system_type = get_pch_platform_type(), .tseg_size = CONFIG_SMM_TSEG_SIZE, .ddr_refresh_2x = CONFIG(ENABLE_DDR_2X_REFRESH), .max_ddr3_freq = 1600,