Change in coreboot[master]: soc/intel/common/block/cpu/car/cache_as_ram: Fix compilation on x86_64
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48170 )
Change subject: soc/intel/common/block/cpu/car/cache_as_ram: Fix compilation on x86_64 ......................................................................
soc/intel/common/block/cpu/car/cache_as_ram: Fix compilation on x86_64
Change-Id: I1b36ca8816dab9d30754aadd230c136978e3b344 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/48170/1
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 5af1fc6..167342f 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -9,6 +9,7 @@ #include <rules.h> #include <intelblocks/msr.h>
+.code32 .global bootblock_pre_c_entry bootblock_pre_c_entry:
@@ -161,6 +162,15 @@ /* Need to align stack to 16 bytes at call instruction. Account for the two pushes below. */ andl $0xfffffff0, %esp + +#if ENV_X86_64 + #include <cpu/x86/64bit/entry64.inc> + movd %mm2, %rdi + shlq $32, %rdi + movd %mm1, %rsi + or %rsi, %rdi + movd %mm0, %rsi +#else sub $8, %esp
/* push TSC value to stack */ @@ -168,6 +178,7 @@ pushl %eax /* tsc[63:32] */ movd %mm1, %eax pushl %eax /* tsc[31:0] */ +#endif
before_carstage: post_code(0x2A)
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48170 )
Change subject: soc/intel/common/block/cpu/car/cache_as_ram: Fix compilation on x86_64 ......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/48170/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48170/1//COMMIT_MSG@7 PS1, Line 7: Fix compilation on x86_64 Maybe: Add x86_64 support?
Hello build bot (Jenkins), Arthur Heymans, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48170
to look at the new patch set (#2).
Change subject: soc/intel/common/block/cpu/car/cache_as_ram: Add x86_64 support ......................................................................
soc/intel/common/block/cpu/car/cache_as_ram: Add x86_64 support
Doesn't affect x86_32. Tested on Intel Skylake. Boots into bootblock and console is working.
Change-Id: I1b36ca8816dab9d30754aadd230c136978e3b344 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/48170/2
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48170 )
Change subject: soc/intel/common/block/cpu/car/cache_as_ram: Add x86_64 support ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48170/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/48170/1//COMMIT_MSG@7 PS1, Line 7: Fix compilation on x86_64
Maybe: Add x86_64 support?
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48170 )
Change subject: soc/intel/common/block/cpu/car/cache_as_ram: Add x86_64 support ......................................................................
Patch Set 2: Code-Review+2
Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48170 )
Change subject: soc/intel/common/block/cpu/car/cache_as_ram: Add x86_64 support ......................................................................
soc/intel/common/block/cpu/car/cache_as_ram: Add x86_64 support
Doesn't affect x86_32. Tested on Intel Skylake. Boots into bootblock and console is working.
Change-Id: I1b36ca8816dab9d30754aadd230c136978e3b344 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/48170 Reviewed-by: Angel Pons th3fanbus@gmail.com Reviewed-by: Arthur Heymans arthur@aheymans.xyz Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/common/block/cpu/car/cache_as_ram.S 1 file changed, 11 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved
diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 5af1fc6..167342f 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -9,6 +9,7 @@ #include <rules.h> #include <intelblocks/msr.h>
+.code32 .global bootblock_pre_c_entry bootblock_pre_c_entry:
@@ -161,6 +162,15 @@ /* Need to align stack to 16 bytes at call instruction. Account for the two pushes below. */ andl $0xfffffff0, %esp + +#if ENV_X86_64 + #include <cpu/x86/64bit/entry64.inc> + movd %mm2, %rdi + shlq $32, %rdi + movd %mm1, %rsi + or %rsi, %rdi + movd %mm0, %rsi +#else sub $8, %esp
/* push TSC value to stack */ @@ -168,6 +178,7 @@ pushl %eax /* tsc[63:32] */ movd %mm1, %eax pushl %eax /* tsc[31:0] */ +#endif
before_carstage: post_code(0x2A)
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)
-
Patrick Rudolph (Code Review)