Change in coreboot[master]: Revert "src/soc/intel/cannonlake: Update C-state latency control limits" - coreboot-gerrit

3 Aug 2021


      Attention is currently required from: Bora Guvendik,  Felix Singer, Lijian Zhao, Shaunak Saha, Nico Huber, Martin Roth, Tim Wawrzynczak, Vaibhav Shankar, Aaron Durbin, Patrick Rudolph.
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56662 )
Change subject: Revert "src/soc/intel/cannonlake: Update C-state latency control limits"
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Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56662/comment/a20c6d0a_3f6ebcea 
PS1, Line 14:
...
S0ix is enabled by default on all recent chromeOs platfroms. […]
Sure :-) I wanted to know if it still works with this change. Also, this should be added to the commit msg
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iea56c6a29ca4b34c9852393fed2e3be4de128ec6
Gerrit-Change-Number: 56662
Gerrit-PatchSet: 1
Gerrit-Owner:  Felix Singer felixsinger@posteo.net
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