Change in coreboot[master]: soc/intel/adl-n: Add device ID for TCSS XHCI

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62955 )

Change subject: soc/intel/adl-n: Add device ID for TCSS XHCI
......................................................................

soc/intel/adl-n: Add device ID for TCSS XHCI

This patch adds TCSS XHCI device ID for ADL-N PCH which is required
for USB3 port enumeration.

BUG=None
BRANCH=None
TEST=Check if device is detected correctly and ACPI entries are generated
for device 0d.0

Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674
Signed-off-by: Maulik V Vaghela 
---
M src/include/device/pci_ids.h
M src/soc/intel/common/block/usb4/xhci.c
2 files changed, 2 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/62955/1

diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index d1365f4..ff7d69a 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4131,6 +4131,7 @@
 #define PCI_DID_INTEL_ADP_P_XHCI		0x51ed
 #define PCI_DID_INTEL_ADP_S_XHCI		0x7ae0
 #define PCI_DID_INTEL_ADP_TCSS_XHCI		0x461e
+#define PCI_DID_INTEL_ADP_N_TCSS_XHCI		0x464e
 #define PCI_DID_INTEL_ADP_M_XHCI		0x54ed
 #define PCI_DID_INTEL_MTL_XHCI			0x7e7d
 #define PCI_DID_INTEL_MTL_M_TCSS_XHCI		0x7eb0
diff --git a/src/soc/intel/common/block/usb4/xhci.c b/src/soc/intel/common/block/usb4/xhci.c
index 64e5601..20ed2a5 100644
--- a/src/soc/intel/common/block/usb4/xhci.c
+++ b/src/soc/intel/common/block/usb4/xhci.c
@@ -31,6 +31,7 @@
    PCI_DID_INTEL_TGP_TCSS_XHCI,
    PCI_DID_INTEL_TGP_H_TCSS_XHCI,
    PCI_DID_INTEL_ADP_TCSS_XHCI,
+	PCI_DID_INTEL_ADP_N_TCSS_XHCI,
    0
 };