Attention is currently required from: Jamie Ryu, Wonkyu Kim, Ethan Tsao, Ravishankar Sarawadi, Paul Menzel, Rizwan Qureshi, Tim Wawrzynczak, Patrick Rudolph. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62581 )
Change subject: soc/intel/common: Include Meteor Lake device IDs ......................................................................
Patch Set 6: Code-Review+2
(2 comments)
File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/62581/comment/5f157890_7d6fad6b PS1, Line 3431: #define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP9 0x7e4d : #define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP10 0x7eca : #define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP11 0x7ecb : #define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP12 0x7ecc
There is no CPU RPs in MTL. All RPs are in SOC/IOE die and FSP UPD is using same array for RP1- RP12;FSP handles like PCH RPs.
So, We can use like below based on location. PCI_DEVICE_ID_INTEL_MTP_SOC_PCIE_RP1-9 PCI_DEVICE_ID_INTEL_MTP_IOE_P_PCIE_RP10-12
Got it, yes this align with EDS as well.
So, with MTL, we are reducing the RPs from 16 (12 PCH and 4 CPU) to 12 (alone).
can we rename the macro to reflect the MTL SoC block diagram proper as something like this:
PCI_DEVICE_ID_INTEL_MTP_SOC_PCIE_RP1-9 PCI_DEVICE_ID_INTEL_MTP_IOE_P_PCIE_RP1-3
https://review.coreboot.org/c/coreboot/+/62581/comment/bc892f7a_79baa0d3 PS1, Line 3962: #define PCI_DEVICE_ID_INTEL_SIMICS_GT0 0xffff
It's used for report platform for early SOC without IGD. We'll define and use in soc folder.
what is the value of showing something that is 0xffff
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Subrata Banik (Code Review)