Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40415 )
Change subject: mb/google/puff: add a region to cache SPD data
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Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40415/7/src/mainboard/google/hatch/...
File src/mainboard/google/hatch/Kconfig:
https://review.coreboot.org/c/coreboot/+/40415/7/src/mainboard/google/hatch/...
PS7, Line 82: if ROMSTAGE_SPD_CBFS
Add something like USE_SPD_CACHE config should be better.
I think how it is at the moment makes more sense. The baseboard has two paths, one for cbfs for downed dimm's while the other smbus for socketted. I don't see why we would need yet another kconfig param since we wouldn't want to not have the spd cache enabled in the smbus path.
We could however have something like:
default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB-spd.fmd" if BOARD_ROMSIZE_KB_16384 && ROMSTAGE_SPD_SMBUS
..
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