Change in coreboot[master]: soc/intel/tgl: Add SkipCpuReplacementCheck to chip options

[Jamie Ryu (Code Review)]

Jamie Ryu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42788 )

Change subject: soc/intel/tgl: Add SkipCpuReplacementCheck to chip options
......................................................................

soc/intel/tgl: Add SkipCpuReplacementCheck to chip options

Add SkipCpuReplacementCheck to chip options to control UPD FSPM
SkipCpuReplacementCheck from device tree.
This UPD allows to skip CPU replacement check to avoid forced MRC
traning with platforms with soldered down SoC.

TEST=boot and verified with volteer

Change-Id: Ic5782723ac3a204f2af657fac9944fb41fc03f4d
Signed-off-by: Jamie Ryu 
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
2 files changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/42788/1

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index c72698f..432f857 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -365,6 +365,12 @@
    	/* External Vnn Voltage in mV */
    	int vnn_sx_voltage_mv;
    } ext_fivr_settings;
+
+	/*
+	 * Enable(0)/Disable(1) CPU Replacement check.
+	 * Default 0. Setting this to 1 skips checking CPU replacement.
+	 */
+	uint8_t SkipCpuReplacementCheck;
 };

typedef struct soc_intel_tigerlake_config config_t;
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 1a46b7a..3eba69a 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -199,6 +199,9 @@

/* Command Pins Mirrored */
    m_cfg->CmdMirror[0] = config->CmdMirror;
+
+	/* Skip CPU replacement check */
+	m_cfg->SkipCpuReplacementCheck = config->SkipCpuReplacementCheck;
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)

Change in coreboot[master]: soc/intel/tigerlake: Add SkipCpuReplacementCheck to chip options

[Jamie Ryu (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/42788

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: Add SkipCpuReplacementCheck to chip options
......................................................................

soc/intel/tigerlake: Add SkipCpuReplacementCheck to chip options

Add SkipCpuReplacementCheck to chip options to control UPD FSPM
SkipCpuReplacementCheck from device tree.
This UPD allows to skip CPU replacement check to avoid forced MRC
traning with platforms with soldered down SoC.

TEST=boot and verified with volteer

Change-Id: Ic5782723ac3a204f2af657fac9944fb41fc03f4d
Signed-off-by: Jamie Ryu 
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
2 files changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/42788/2

Change in coreboot[master]: soc/intel/tigerlake: Add SkipCpuReplacementCheck to chip options

[Wonkyu Kim (Code Review)]

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42788 )

Change subject: soc/intel/tigerlake: Add SkipCpuReplacementCheck to chip options
......................................................................

Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/42788/2/src/soc/intel/tigerlake/chi... 
File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/42788/2/src/soc/intel/tigerlake/chi... 
PS2, Line 369: 	/*
             : 	 * Enable(0)/Disable(1) CPU Replacement check.
             : 	 * Default 0. Setting this to 1 skips checking CPU replacement.
             : 	 */
             : 	uint8_t SkipCpuReplacementCheck;
I think most of time it should be skipped in platform.
Is there any specific case we need to disable?  I think it may requires RVP case which has CPU socket.  In that case, can we use DisableSkipCpuReplacementCheck so that we don't need to change in each devicetree change?

Change in coreboot[master]: soc/intel/tigerlake: Add CpuReplacementCheck to chip options

[Jamie Ryu (Code Review)]

Hello Shaunak Saha, build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Duncan Laurie, Paul Menzel, Rizwan Qureshi, Angel Pons, Sridhar Siricilla, Patrick Rudolph, V Sowmya, Nick Vaccaro, Srinidhi N Kaushik, Raj Astekar,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/42788

to look at the new patch set (#3).

Change subject: soc/intel/tigerlake: Add CpuReplacementCheck to chip options
......................................................................

soc/intel/tigerlake: Add CpuReplacementCheck to chip options

Add CpuReplacementCheck to chip options to control UPD FSPM
SkipCpuReplacementCheck from devicetree.
This UPD allows platforms with soldered down SoC to skip CPU
replacement check to avoid a forced MRC traning.

TEST=boot and verified with volteer

Change-Id: Ic5782723ac3a204f2af657fac9944fb41fc03f4d
Signed-off-by: Jamie Ryu 
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
2 files changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/42788/3

Change in coreboot[master]: soc/intel/tigerlake: Add CpuReplacementCheck to chip options

[Jamie Ryu (Code Review)]

Jamie Ryu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42788 )

Change subject: soc/intel/tigerlake: Add CpuReplacementCheck to chip options
......................................................................

Patch Set 3: Code-Review+1

(1 comment)

https://review.coreboot.org/c/coreboot/+/42788/2/src/soc/intel/tigerlake/chi... 
File src/soc/intel/tigerlake/chip.h:

https://review.coreboot.org/c/coreboot/+/42788/2/src/soc/intel/tigerlake/chi... 
PS2, Line 369: 	/*
             : 	 * Enable(0)/Disable(1) CPU Replacement check.
             : 	 * Default 0. Setting this to 1 skips checking CPU replacement.
             : 	 */
             : 	uint8_t SkipCpuReplacementCheck;
> I think most of time it should be skipped in platform. […]

I agree with your point and made changes at patch #3. 
Please review and let me know your comments. Thank you.

Change in coreboot[master]: soc/intel/tigerlake: Add CpuReplacementCheck to chip options

[Nick Vaccaro (Code Review)]

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42788 )

Change subject: soc/intel/tigerlake: Add CpuReplacementCheck to chip options
......................................................................

Patch Set 3: Code-Review+2

Change in coreboot[master]: soc/intel/tigerlake: Add CpuReplacementCheck to chip options

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/42788 )

Change subject: soc/intel/tigerlake: Add CpuReplacementCheck to chip options
......................................................................

soc/intel/tigerlake: Add CpuReplacementCheck to chip options

Add CpuReplacementCheck to chip options to control UPD FSPM
SkipCpuReplacementCheck from devicetree.
This UPD allows platforms with soldered down SoC to skip CPU
replacement check to avoid a forced MRC traning.

TEST=boot and verified with volteer

Change-Id: Ic5782723ac3a204f2af657fac9944fb41fc03f4d
Signed-off-by: Jamie Ryu 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42788
Reviewed-by: Nick Vaccaro 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
2 files changed, 9 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nick Vaccaro: Looks good to me, approved
  Jamie Ryu: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h
index c72698f..26ed64e 100644
--- a/src/soc/intel/tigerlake/chip.h
+++ b/src/soc/intel/tigerlake/chip.h
@@ -365,6 +365,12 @@
    	/* External Vnn Voltage in mV */
    	int vnn_sx_voltage_mv;
    } ext_fivr_settings;
+
+	/*
+	 * Enable(1)/Disable(0) CPU Replacement check.
+	 * Default 0. Setting this to 1 to check CPU replacement.
+	 */
+	uint8_t CpuReplacementCheck;
 };

typedef struct soc_intel_tigerlake_config config_t;
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 1a46b7a..1f60b52 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -199,6 +199,9 @@

/* Command Pins Mirrored */
    m_cfg->CmdMirror[0] = config->CmdMirror;
+
+	/* Skip CPU replacement check */
+	m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck;
 }

void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)