Attention is currently required from: Jason Glenesk, Marshall Dawson, Felix Held. Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59499 )
Change subject: vc/amd/fsp/cezanne: Update UPDs to 1.0.4r3 ......................................................................
vc/amd/fsp/cezanne: Update UPDs to 1.0.4r3
This change adds the gop_edp_init_delay and void_function parameters.
BUG=b:179699789 TEST=Build guybrush
Signed-off-by: Raul E Rangel rrangel@chromium.org Change-Id: I01a7e24ac360c7c7a5af46f4e5347b882d62f1cc --- M src/vendorcode/amd/fsp/cezanne/FspmUpd.h M src/vendorcode/amd/fsp/cezanne/FspsUpd.h 2 files changed, 6 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/59499/1
diff --git a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h index f21ca42..0357eaa 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspmUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspmUpd.h @@ -27,7 +27,8 @@ /** Offset 0x007C**/ uint32_t serial_reserved; /** Offset 0x0080**/ uint8_t dxio_descriptor[FSPM_UPD_DXIO_DESCRIPTOR_COUNT][52]; /** Offset 0x0358**/ uint8_t fsp_owns_pcie_resets; - /** Offset 0x0359**/ uint8_t pcie_reserved[51]; + /** Offset 0x0359**/ uint32_t void_function; + /** Offset 0x035D**/ uint8_t pcie_reserved[47]; /** Offset 0x038C**/ uint32_t ddi_descriptor[FSPM_UPD_DDI_DESCRIPTOR_COUNT]; /** Offset 0x03A0**/ uint8_t ddi_reserved[6]; /** Offset 0x03A6**/ uint8_t ccx_down_core_mode; diff --git a/src/vendorcode/amd/fsp/cezanne/FspsUpd.h b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h index 3ac52c0..0bb3343 100644 --- a/src/vendorcode/amd/fsp/cezanne/FspsUpd.h +++ b/src/vendorcode/amd/fsp/cezanne/FspsUpd.h @@ -11,8 +11,10 @@
typedef struct __packed { /** Offset 0x0020**/ uint32_t vbios_buffer; - /** Offset 0x0024**/ uint64_t gop_reserved; - /** Offset 0x002C**/ uint32_t reserved1; + /** Offset 0x0024**/ uint16_t gop_edp_init_delay; + /** Offset 0x0026**/ uint16_t gop_reserved1; + /** Offset 0x0028**/ uint32_t gop_reserved2; + /** Offset 0x002C**/ uint32_t void_function; /** Offset 0x0030**/ uint16_t UpdTerminator; } FSP_S_CONFIG;