Change in coreboot[master]: soc/intel/denverton_ns: Fix MRC_RW_CACHE

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60091 )

Change subject: soc/intel/denverton_ns: Fix MRC_RW_CACHE
......................................................................

soc/intel/denverton_ns: Fix MRC_RW_CACHE

It is required to set WPD (Write Protect Disable) bit
to make it possible to use MRC_RW_CACHE region with
CACHE_MRC_SETTINGS=y.

Change-Id: Iacab44b00d08c9bdc18bc3bdcb88833634c0b02e
Signed-off-by: Kyösti Mälkki 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60091
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/soc/intel/denverton_ns/bootblock/bootblock.c
1 file changed, 1 insertion(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c
index cb2503a..0846c8e 100644
--- a/src/soc/intel/denverton_ns/bootblock/bootblock.c
+++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c
@@ -84,6 +84,7 @@
 #if (CONFIG(CONSOLE_SERIAL))
    early_uart_init();
 #endif
+	fast_spi_early_init(DEFAULT_SPI_BASE);
 };

void bootblock_soc_init(void)