[M] Change in coreboot[main]: soc/intel/xeon_sp/skx: Configure IOAPICs

[Lean Sheng Tan (Code Review)]

Attention is currently required from: Alicja Michalska, Angel Pons, Christian Walter, Eric Lai, Felix Held, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Tim Chu, [e-mail].

Lean Sheng Tan has uploaded a new patch set (#12) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85170?usp=email )

Change subject: soc/intel/xeon_sp/skx: Configure IOAPICs
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soc/intel/xeon_sp/skx: Configure IOAPICs

FSP only configures the PCH IOAPIC. Let coreboot reconfigure all
IOAPICs to assign unique IDs to each. Every IOAPIC has 8 GSIs, and the
IOAPICs on Socket1 start at GSI 72, thus calculate the exact GSI
address for each IOAPIC instead of assume it's a linear address space.

Unselect XEON_SP_HAVE_IIO_IOAPIC to prevent soc_get_ioapic_info()
from advertising wrong GSI addresses.

TEST: Booted on ocp/tiogapass with correct GSI bases asigned
      matching the _PRT advertised GSI bases.

Xeon Skylake-SP IOAPIC is the same as used on Intel Xeon E7 v2.
See Document Reference Number: 329595-002

Change-Id: I3bd69e6293b1994a4b3a49361fa7eb45cc0a3a5f
Signed-off-by: Patrick Rudolph 
---
M src/soc/intel/xeon_sp/lpc_gen1.c
M src/soc/intel/xeon_sp/skx/Kconfig
M src/soc/intel/xeon_sp/skx/Makefile.mk
A src/soc/intel/xeon_sp/skx/ioapic.c
4 files changed, 74 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/85170/12