[M] Change in coreboot[master]: soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS

[Meera Ravindranath (Code Review)]

Attention is currently required from: Subrata Banik, Haribalaraman Ramasubramanian, Reka Norman, Rizwan Qureshi, Tim Wawrzynczak, Daniil Lunev, Nick Vaccaro, Divagar Mohandass.

Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68251 )

Change subject: soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS
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Patch Set 9:

(3 comments)

File src/soc/intel/alderlake/include/soc/ufs.h:

https://review.coreboot.org/c/coreboot/+/68251/comment/75bfc3b1_0d7a1bb3 
PS8, Line 26: 0x1B0C
> 0x1b0c

Done

https://review.coreboot.org/c/coreboot/+/68251/comment/64d0a8af_84da8e04 
PS8, Line 27: 0x1E30
> 0x1e30

Done

File src/soc/intel/common/block/acpi/acpi/ufs.asl:

https://review.coreboot.org/c/coreboot/+/68251/comment/8b4df17c_d9cf9e6b 
PS8, Line 67: PCH_PWRM_BASE_SIZE
> nit: won't this fit in line above?

Done