[S] Change in coreboot[master]: soc/amd/phoenix/include/xhci: add USB4 XHCI device pointers

[Robert Zieba (Code Review)]

Attention is currently required from: Jason Glenesk, Matt DeVillier, Martin Roth, Fred Reitberger, Karthik Ramasubramanian, Felix Held.

Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74658 )

Change subject: soc/amd/phoenix/include/xhci: add USB4 XHCI device pointers
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Patch Set 2:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/74658/comment/f0d9d9f6_edcd2929 
PS2, Line 9: Beware that there's no XHCI2 controller and the USB4 controller device
           : pointers were added right after the xhci_0 and xhci_1 controller device
           : pointers.
> ah, ok, wasn't sure about this requirement of the xhci pci code; pinged Robert to look into that. […]

The relevant code just doesn't support holes in the device list. In particular, the XHCI wake event logging code uses the PCI resources that are stored in SMRAM. The resource store code has no concept of gaps in the device list, nor should it IMHO. So any change would have to be done in the XHCI-specific code.

The XHCI wake events in the elog do use the index into `SOC_XHCI_DEVICES` as the XHCI controller number. So that could be confusing if we did ever have both an `xhci_2` and `usb4_xhci_0`. But overall, I don't think that's a big issue.