[S] Change in coreboot[main]: soc/intel/common/gpio: add function to lock GPIO configuration

[Subrata Banik (Code Review)]

Attention is currently required from: Bora Guvendik, Cliff Huang, Jérémy Compostella, Pranava Y N.

Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84901?usp=email )

Change subject: soc/intel/common/gpio: add function to lock GPIO configuration
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Patch Set 3:

(1 comment)

File src/soc/intel/common/block/gpio/gpio.c:

https://review.coreboot.org/c/coreboot/+/84901/comment/70805255_ec6fa45c?usp... :
PS3, Line 485: /* Clear lock for the exception PADs */
> Locked pads still function as it is configured, just that we won't be able to change the configuration afterwards (i.e. dp & OS). There is also TX state lock bit(s) in separate registers, but we don't consider locking those output for a selected GPOs.

my points is even w/o these two cls, when we have marked any PAD as lock config, we won't be able to change the PAD configuration post FSP_S, unless we are in SMM. I don't follow what value this CL is bringing?