Change in coreboot[master]: soc/intel/common/block/pcie: Add ADL-P CPU PCIe Device IDs

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Tracy Wu, Patrick Rudolph.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59081 )

Change subject: soc/intel/common/block/pcie: Add ADL-P CPU PCIe Device IDs
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Patch Set 2: Code-Review+1

(1 comment)

Patchset:

PS2: 
couple questions:
1) Are the LTR snoop values the same for the PEG ports?
2) Are the init steps here supposed to be the same, any changes req'd?