Change in coreboot[master]: mb/google/brya/var/taeko: Add judgment for PCIE signal switch

[Kevin Chang (Code Review)]

Kevin Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60341 )

Change subject: mb/google/brya/var/taeko: Add judgment for PCIE signal switch
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mb/google/brya/var/taeko: Add judgment for PCIE signal switch

Taeko will using two PCIE port singal with one slot, one CLK and one CLKREQ
that need add judgment in overridetree.cb.

BUG=b:211914322
TEST=Test on takeo trace in FSP log can found setting correct

Signed-off-by: Kevin Chang 
Change-Id: I4486f23ea02374c84a9b1ce04f568d78aeabd573
---
M src/mainboard/google/brya/variants/taeko/overridetree.cb
1 file changed, 17 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/60341/1

diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb
index b82e9de..7c93854 100644
--- a/src/mainboard/google/brya/variants/taeko/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb
@@ -237,6 +237,7 @@
    			.clk_req = 0,
    			.clk_src = 0,
    		}"
+			probe BOOT_NVME_MASK BOOT_NVME_ENABLED
    	end
    	device ref tbt_pcie_rp0 off end
    	device ref tbt_pcie_rp1 off end
@@ -391,13 +392,26 @@
    			end
    		end
    	end
-		device ref pcie_rp9 on
+		device ref pcie_rp9 off	end
+		device ref pcie_rp12 on
+			# Enable NVMe PCIE 12 using clk 0
+			register "pch_pcie_rp[PCH_RP(12)]" = "{
+				.clk_src = 0,
+				.clk_req = 0,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
+			}"
+			device generic 0 on
+				probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED
+			end
    		chip soc/intel/common/block/pcie/rtd3
    			register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)"
    			register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B4)"
-				register "srcclk_pin" = "1"
-				device generic 0 on end
+				register "srcclk_pin" = "0"
+				device generic 0 on
+					probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED
+				end
    		end
+			probe BOOT_EMMC_MASK BOOT_EMMC_ENABLED
    	end
    	device ref gspi1 on
    		chip drivers/spi/acpi