Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41070 )
Change subject: soc/amd/common/block/lpc: Reorganize LPC enable resources ......................................................................
soc/amd/common/block/lpc: Reorganize LPC enable resources
This change moves all the logic for setting up decode windows for LPC under configure_child_lpc_windows() which is called from lpc_enable_children_resources(). This is in preparation to configure decode windows for eSPI differently if mainboard decides to use eSPI instead of LPC.
BUG=b:154445472
Change-Id: Ib8275bc4ce51cd8afd390901ac723ce71c7a9148 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 25 insertions(+), 33 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/41070/1
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 54befef..aa23e7b 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -146,13 +146,17 @@ pci_dev_set_resources(dev); }
-static void set_child_resource(struct device *dev, struct device *child, - u32 *reg, u32 *reg_x) +static void configure_child_lpc_windows(struct device *dev, struct device *child) { struct resource *res; u32 base, end; u32 rsize = 0, set = 0, set_x = 0; int wideio_index; + u32 reg, reg_x; + + reg = pci_read_config32(dev, LPC_IO_PORT_DECODE_ENABLE); + reg_x = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); +
/* * Be a bit relaxed, tolerate that LPC region might be bigger than @@ -249,16 +253,12 @@ } /* check if region found and matches the enable */ if (res->size <= rsize) { - *reg |= set; - *reg_x |= set_x; + reg |= set; + reg_x |= set_x; /* check if we can fit resource in variable range */ } else { wideio_index = lpc_set_wideio_range(base, res->size); if (wideio_index != WIDEIO_RANGE_ERROR) { - /* preserve wide IO related bits. */ - *reg_x = pci_read_config32(dev, - LPC_IO_OR_MEM_DECODE_ENABLE); - printk(BIOS_DEBUG, "Range assigned to wide IO %d\n", wideio_index); @@ -271,39 +271,31 @@ } } } -}
-/** - * @brief Enable resources for children devices - * - * @param dev the device whose children's resources are to be enabled - * - */ -static void lpc_enable_childrens_resources(struct device *dev) -{ - struct bus *link; - u32 reg, reg_x; - - reg = pci_read_config32(dev, LPC_IO_PORT_DECODE_ENABLE); - reg_x = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); - - for (link = dev->link_list; link; link = link->next) { - struct device *child; - for (child = link->children; child; - child = child->sibling) { - if (child->enabled - && (child->path.type == DEVICE_PATH_PNP)) - set_child_resource(dev, child, ®, ®_x); - } - } pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, reg); pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, reg_x); }
+static void lpc_enable_children_resources(struct device *dev) +{ + struct bus *link; + struct device *child; + + for (link = dev->link_list; link; link = link->next) { + for (child = link->children; child; child = child->sibling) { + if (!child->enabled) + continue; + if (child->path.type != DEVICE_PATH_PNP) + continue; + configure_child_lpc_windows(dev, child); + } + } +} + static void lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); - lpc_enable_childrens_resources(dev); + lpc_enable_children_resources(dev); }
static struct device_operations lpc_ops = {
Furquan Shaikh has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/41070 )
Change subject: soc/amd/common/block/lpc: Reorganize LPC enable resources ......................................................................
soc/amd/common/block/lpc: Reorganize LPC enable resources
This change moves all the logic for setting up decode windows for LPC under configure_child_lpc_windows() which is called from lpc_enable_children_resources(). This is in preparation to configure decode windows for eSPI differently if mainboard decides to use eSPI instead of LPC.
Side-effect of this change is that the IO decode registers are written after each child device resources are considered.
BUG=b:154445472
Change-Id: Ib8275bc4ce51cd8afd390901ac723ce71c7a9148 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 27 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/41070/2
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41070
to look at the new patch set (#3).
Change subject: soc/amd/common/block/lpc: Reorganize LPC enable resources ......................................................................
soc/amd/common/block/lpc: Reorganize LPC enable resources
This change moves all the logic for setting up decode windows for LPC under configure_child_lpc_windows() which is called from lpc_enable_children_resources(). This is in preparation to configure decode windows for eSPI differently if mainboard decides to use eSPI instead of LPC.
Side-effect of this change is that the IO decode registers are written after each child device resources are considered.
BUG=b:154445472
Change-Id: Ib8275bc4ce51cd8afd390901ac723ce71c7a9148 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 26 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/41070/3
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41070 )
Change subject: soc/amd/common/block/lpc: Reorganize LPC enable resources ......................................................................
Patch Set 3: Code-Review+2
Hello build bot (Jenkins), Raul Rangel, Aaron Durbin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41070
to look at the new patch set (#5).
Change subject: soc/amd/common/block/lpc: Reorganize LPC enable resources ......................................................................
soc/amd/common/block/lpc: Reorganize LPC enable resources
This change moves all the logic for setting up decode windows for LPC under configure_child_lpc_windows() which is called from lpc_enable_children_resources(). This is in preparation to configure decode windows for eSPI differently if mainboard decides to use eSPI instead of LPC.
Side-effect of this change is that the IO decode registers are written after each child device resources are considered.
BUG=b:154445472
Change-Id: Ib8275bc4ce51cd8afd390901ac723ce71c7a9148 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 26 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/41070/5
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41070 )
Change subject: soc/amd/common/block/lpc: Reorganize LPC enable resources ......................................................................
Patch Set 5: Code-Review+2
Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41070 )
Change subject: soc/amd/common/block/lpc: Reorganize LPC enable resources ......................................................................
soc/amd/common/block/lpc: Reorganize LPC enable resources
This change moves all the logic for setting up decode windows for LPC under configure_child_lpc_windows() which is called from lpc_enable_children_resources(). This is in preparation to configure decode windows for eSPI differently if mainboard decides to use eSPI instead of LPC.
Side-effect of this change is that the IO decode registers are written after each child device resources are considered.
BUG=b:154445472
Change-Id: Ib8275bc4ce51cd8afd390901ac723ce71c7a9148 Signed-off-by: Furquan Shaikh furquan@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/41070 Reviewed-by: Aaron Durbin adurbin@chromium.org Reviewed-by: Raul Rangel rrangel@chromium.org Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 26 insertions(+), 31 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 4b217ae..1e57bc0 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -145,13 +145,17 @@ pci_dev_set_resources(dev); }
-static void set_child_resource(struct device *dev, struct device *child, - u32 *reg, u32 *reg_x) +static void configure_child_lpc_windows(struct device *dev, struct device *child) { struct resource *res; u32 base, end; u32 rsize = 0, set = 0, set_x = 0; int wideio_index; + u32 reg, reg_x; + + reg = pci_read_config32(dev, LPC_IO_PORT_DECODE_ENABLE); + reg_x = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); +
/* * Be a bit relaxed, tolerate that LPC region might be bigger than @@ -248,16 +252,15 @@ } /* check if region found and matches the enable */ if (res->size <= rsize) { - *reg |= set; - *reg_x |= set_x; + reg |= set; + reg_x |= set_x; /* check if we can fit resource in variable range */ } else { wideio_index = lpc_set_wideio_range(base, res->size); if (wideio_index != WIDEIO_RANGE_ERROR) { /* preserve wide IO related bits. */ - *reg_x = pci_read_config32(dev, + reg_x = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); - printk(BIOS_DEBUG, "Range assigned to wide IO %d\n", wideio_index); @@ -270,39 +273,31 @@ } } } -}
-/** - * @brief Enable resources for children devices - * - * @param dev the device whose children's resources are to be enabled - * - */ -static void lpc_enable_childrens_resources(struct device *dev) -{ - struct bus *link; - u32 reg, reg_x; - - reg = pci_read_config32(dev, LPC_IO_PORT_DECODE_ENABLE); - reg_x = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); - - for (link = dev->link_list; link; link = link->next) { - struct device *child; - for (child = link->children; child; - child = child->sibling) { - if (child->enabled - && (child->path.type == DEVICE_PATH_PNP)) - set_child_resource(dev, child, ®, ®_x); - } - } pci_write_config32(dev, LPC_IO_PORT_DECODE_ENABLE, reg); pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, reg_x); }
+static void lpc_enable_children_resources(struct device *dev) +{ + struct bus *link; + struct device *child; + + for (link = dev->link_list; link; link = link->next) { + for (child = link->children; child; child = child->sibling) { + if (!child->enabled) + continue; + if (child->path.type != DEVICE_PATH_PNP) + continue; + configure_child_lpc_windows(dev, child); + } + } +} + static void lpc_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); - lpc_enable_childrens_resources(dev); + lpc_enable_children_resources(dev); }
static struct device_operations lpc_ops = {
-
Aaron Durbin (Code Review) -
Furquan Shaikh (Code Review)
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Raul Rangel (Code Review)