Change in coreboot[master]: soc/intel/alderlake:[TEST] Enable PMC trace

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60000 )

Change subject: soc/intel/alderlake:[TEST] Enable PMC trace
......................................................................

soc/intel/alderlake:[TEST] Enable PMC trace

The patch enables PMC trace. It shouldn't be enabled on production
systems

Signed-off-by: Sridhar Siricilla 
Change-Id: Id4d5189683202dd5e31ad21deb5c1cbc4581c478
---
M src/soc/intel/alderlake/fsp_params.c
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/60000/1

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 251b252..51ea738 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -696,6 +696,12 @@
    printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n");
 }

+static void fill_fsps_dbg_params(FSP_S_CONFIG *s_cfg,
+		const struct soc_intel_alderlake_config *config)
+{
+	/* Enables PMC trace */
+	s_cfg->PmcDbgMsgEn = 1;
+}
 static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg,
    	const struct soc_intel_alderlake_config *config)
 {
@@ -788,6 +794,7 @@
    	fill_fsps_fivr_params,
    	fill_fsps_fivr_rfi_params,
    	fill_fsps_acoustic_params,
+		fill_fsps_dbg_params,
    };

for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++)