Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43882 )
Change subject: mb/google/eve: Relocate devicetree FSP settings ......................................................................
mb/google/eve: Relocate devicetree FSP settings
Also drop some redundant comments about these settings.
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I150013c8f7ffea34a215c089f59899cb04a8eb16 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/eve/devicetree.cb 1 file changed, 81 insertions(+), 91 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/43882/1
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index e26128d..76f7cb1 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -36,25 +36,12 @@
# FSP Configuration register "ProbelessTrace" = "0" - register "EnableLan" = "0" - register "EnableSata" = "0" - register "SataSalpSupport" = "0" - register "SataMode" = "0" - register "SataPortsEnable[0]" = "0" - register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "EnableTraceHub" = "0" register "SsicPortEnable" = "0" - register "SmbusEnable" = "1" register "Cio2Enable" = "0" - register "ScsEmmcEnabled" = "1" - register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "0" register "PttSwitch" = "0" register "SkipExtGfxScan" = "1" - register "Device4Enable" = "1" - register "HeciEnabled" = "0" register "SaGv" = "3" register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s @@ -138,25 +125,6 @@ .dc_loadline = 430, }"
- # Enable Root port 1 with SRCCLKREQ1# - register "PcieRpEnable[0]" = "1" - register "PcieRpClkReqSupport[0]" = "1" - register "PcieRpClkReqNumber[0]" = "1" - register "PcieRpAdvancedErrorReporting[0]" = "1" - register "PcieRpLtrEnable[0]" = "1" - register "PcieRpHotPlug[0]" = "1" - #RP 1 uses CLK SRC 1 - register "PcieRpClkSrcNumber[0]" = "1" - - # Enable Root port 5 with SRCCLKREQ4# - register "PcieRpEnable[4]" = "1" - register "PcieRpClkReqSupport[4]" = "1" - register "PcieRpClkReqNumber[4]" = "4" - register "PcieRpAdvancedErrorReporting[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" - #RP 5 uses CLK SRC 4 - register "PcieRpClkSrcNumber[4]" = "4" - register "usb2_ports[0]" = "USB2_PORT_LONG(OC0)" # Type-C Port 1 register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth @@ -169,61 +137,10 @@ register "usb3_ports[2]" = "USB3_PORT_EMPTY" # Empty register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
- # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | - #| I2C0 | Touchscreen | - #| I2C1 | Early TPM access | - #| I2C2 | Touchpad | - #| I2C4 | Audio | - #+-------------------+---------------------------+ register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .i2c[0] = { - .speed = I2C_SPEED_FAST_PLUS, - .rise_time_ns = 98, - .fall_time_ns = 38, - }, - .i2c[1] = { - .early_init = 1, - .speed = I2C_SPEED_FAST, - .rise_time_ns = 112, - .fall_time_ns = 34, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 186, - .scl_hcnt = 93, - .sda_hold = 36, - } - }, - .i2c[4] = { - .speed = I2C_SPEED_FAST, - .speed_config[0] = { - .speed = I2C_SPEED_FAST, - .scl_lcnt = 176, - .scl_hcnt = 95, - .sda_hold = 36, - } - }, }"
- # Touchscreen - register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" - - # Enable I2C1 bus early for TPM access - register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" - - # Touchpad - register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" - - # Audio - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -253,6 +170,10 @@ device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device + + # FIXME: corresponding device entry is missing + register "Device4Enable" = "1" + device pci 14.0 on chip drivers/usb/acpi register "desc" = ""Root Hub"" @@ -303,6 +224,12 @@ device pci 14.1 off end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem device pci 15.0 on + register "i2c_voltage[0]" = "I2C_VOLTAGE_3V3" + register "common_soc_config.i2c[0]" = "{ + .speed = I2C_SPEED_FAST_PLUS, + .rise_time_ns = 98, + .fall_time_ns = 38, + }" chip drivers/i2c/hid register "generic.hid" = ""WCOM50C1"" register "generic.desc" = ""WCOM Digitizer"" @@ -313,6 +240,13 @@ end end # I2C #0 device pci 15.1 on + register "i2c_voltage[1]" = "I2C_VOLTAGE_3V3" + register "common_soc_config.i2c[1]" = "{ + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 112, + .fall_time_ns = 34, + }" chip drivers/i2c/tpm register "hid" = ""GOOG0005"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" @@ -320,6 +254,16 @@ end end # I2C #1 device pci 15.2 on + register "i2c_voltage[2]" = "I2C_VOLTAGE_1V8" + register "common_soc_config.i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 186, + .scl_hcnt = 93, + .sda_hold = 36, + }, + }" chip drivers/i2c/hid register "generic.hid" = ""ACPI0C50"" register "generic.desc" = ""Touchpad"" @@ -334,15 +278,34 @@ end end # I2C #2 device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 + device pci 16.0 on # Management Engine Interface 1 + + # FIXME: does not match devicetree! + register "HeciEnabled" = "0" + end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 off end # SATA + device pci 17.0 off # SATA + register "EnableSata" = "0" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "0" + end device pci 19.0 on end # UART #2 device pci 19.1 off end # I2C #5 device pci 19.2 on + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" + register "common_soc_config.i2c[4]" = "{ + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 176, + .scl_hcnt = 95, + .sda_hold = 36, + }, + }" chip drivers/i2c/max98927 register "interleave_mode" = "1" register "vmon_slot_no" = "4" @@ -390,6 +353,13 @@ end end # I2C #4 device pci 1c.0 on + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "1" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpHotPlug[0]" = "1" + register "PcieRpClkSrcNumber[0]" = "1" chip drivers/intel/wifi register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end @@ -398,7 +368,14 @@ device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.4 on # PCI Express Port 5 + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "4" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpClkSrcNumber[4]" = "4" + end device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 @@ -418,9 +395,14 @@ end end # GSPI #0 device pci 1e.3 off end # GSPI #1 - device pci 1e.4 on end # eMMC + device pci 1e.4 on # eMMC + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + end device pci 1e.5 off end # SDIO - device pci 1e.6 off end # SDCard + device pci 1e.6 off # SDCard + register "ScsSdCardEnabled" = "0" + end device pci 1f.0 on chip ec/google/chromeec device pnp 0c09.0 on end @@ -428,9 +410,17 @@ end # LPC Interface device pci 1f.1 on end # P2SB device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus + device pci 1f.3 on # Intel HDA + register "EnableAzalia" = "1" + end + device pci 1f.4 on # SMBus + register "SmbusEnable" = "1" + end device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + device pci 1f.6 off # GbE + register "EnableLan" = "0" + end + + register "EnableTraceHub" = "0" end end
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43882 )
Change subject: mb/google/eve: Relocate devicetree FSP settings ......................................................................
Patch Set 1: Code-Review+2
Hello build bot (Jenkins), Michael Niewöhner,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/43882
to look at the new patch set (#2).
Change subject: mb/google/eve: Relocate devicetree settings ......................................................................
mb/google/eve: Relocate devicetree settings
Also drop some redundant comments about these settings.
Tested with BUILD_TIMELESS=1, its coreboot.rom does not change.
Change-Id: I150013c8f7ffea34a215c089f59899cb04a8eb16 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/eve/devicetree.cb 1 file changed, 81 insertions(+), 91 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/43882/2
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43882 )
Change subject: mb/google/eve: Relocate devicetree settings ......................................................................
Abandoned
-
Angel Pons (Code Review) -
Michael Niewöhner (Code Review)