Attention is currently required from: Patrick Rudolph. Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/59310 )
Change subject: soc/intel/../thermal: Use `thermal_rmw32` API for setting LTT ......................................................................
soc/intel/../thermal: Use `thermal_rmw32` API for setting LTT
This patch creates a helper function `thermal_rmw32` to set thermal device Low Temp Threshold (LTT) value.
Also, modified `pch_get_ltt_value()` return type from uint16_t to uint32_t.
TEST=Able to build and boot hatch and adlrvp with this change.
Change-Id: I51fea7bd2146ea29ef476218c006f7350b32c006 Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/common/block/thermal/thermal.c 1 file changed, 12 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/59310/1
diff --git a/src/soc/intel/common/block/thermal/thermal.c b/src/soc/intel/common/block/thermal/thermal.c index 6211f35..df01811 100644 --- a/src/soc/intel/common/block/thermal/thermal.c +++ b/src/soc/intel/common/block/thermal/thermal.c @@ -23,7 +23,7 @@ }
/* PCH Low Temp Threshold (LTT) */ -static uint16_t pch_get_ltt_value(struct device *dev) +static uint32_t pch_get_ltt_value(struct device *dev) { uint8_t thermal_config;
@@ -37,10 +37,19 @@ return GET_LTT_VALUE(thermal_config); }
+static void thermal_rmw32(uintptr_t addr, uint32_t anddata, uint32_t ordata) +{ + uint32_t data32; + + data32 = read32p(addr); + data32 &= anddata; + data32 |= ordata; + write32p(addr, data32); +} + /* Enable thermal sensor power management */ void pch_thermal_configuration(void) { - uint16_t reg16; uintptr_t thermalbar; uintptr_t thermalbar_pm; struct device *dev; @@ -65,9 +74,5 @@ thermalbar_pm = thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT;
/* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */ - reg16 = read16((uint16_t *)thermalbar_pm); - reg16 &= ~CATASTROPHIC_TRIP_POINT_MASK; - /* Low Temp Threshold (LTT) */ - reg16 |= pch_get_ltt_value(dev); - write16((uint16_t *)thermalbar_pm, reg16); + thermal_rmw32(thermalbar_pm, ~CATASTROPHIC_TRIP_POINT_MASK, pch_get_ltt_value(dev)); }