King Sumo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/57033 )
Change subject: soc/intel/denverton_ns: Fix MRC cache write ......................................................................
soc/intel/denverton_ns: Fix MRC cache write
Fast SPI initialization is required for MRC cache write.
Signed-off-by: King Sumo kingsumos@gmail.com Change-Id: I50cc4f8ced0b0524b39eece5a2bb4f0d99fb4eff --- M src/soc/intel/denverton_ns/bootblock/bootblock.c 1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/57033/1
diff --git a/src/soc/intel/denverton_ns/bootblock/bootblock.c b/src/soc/intel/denverton_ns/bootblock/bootblock.c index 76db62e..623cad1 100644 --- a/src/soc/intel/denverton_ns/bootblock/bootblock.c +++ b/src/soc/intel/denverton_ns/bootblock/bootblock.c @@ -8,6 +8,7 @@ #include <soc/iomap.h> #include <spi-generic.h> #include <console/console.h> +#include <intelblocks/fast_spi.h>
const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { @@ -54,6 +55,7 @@ #if (CONFIG(CONSOLE_SERIAL)) early_uart_init(); #endif + fast_spi_early_init(DEFAULT_SPI_BASE); };
void bootblock_soc_init(void)