Change in ...coreboot[master]: soc/intel/apollolake: Add support to log XHCI wake events
Hello Karthikeyan Ramasubramanian,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/32000
to review the following change.
Change subject: soc/intel/apollolake: Add support to log XHCI wake events ......................................................................
soc/intel/apollolake: Add support to log XHCI wake events
Add support to identify and log the XHCI wake events for apollolake into event logs.
BUG=b:123429132 BRANCH=None TEST=Ensure that the system boots to ChromeOS. Ensure that the wake up events due to USB are logged into the event logs. 12 | 2019-03-20 13:36:12 | S0ix Enter 13 | 2019-03-20 13:36:23 | S0ix Exit 14 | 2019-03-20 13:36:23 | Wake Source | PME - XHCI (USB 2.0 port) | 9 15 | 2019-03-20 13:36:23 | Wake Source | GPE # | 13 16 | 2019-03-20 13:36:54 | S0ix Enter 17 | 2019-03-20 13:36:59 | S0ix Exit 18 | 2019-03-20 13:36:59 | Wake Source | PME - XHCI (USB 2.0 port) | 9 19 | 2019-03-20 13:36:59 | Wake Source | GPE # | 13 20 | 2019-03-20 13:38:15 | S0ix Enter 21 | 2019-03-20 13:38:23 | S0ix Exit 22 | 2019-03-20 13:38:23 | Wake Source | PME - XHCI (USB 2.0 port) | 9 23 | 2019-03-20 13:38:23 | Wake Source | GPE # | 13
Change-Id: I55b850646dda8acaa086a9012c2d8b611016f932 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/elog.c 2 files changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/32000/1
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 19cd296..9696245 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -97,6 +97,7 @@ select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_CSE + select SOC_INTEL_COMMON_ELOG_XHCI select UDELAY_TSC select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index b03d5e6..51e4e00 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -19,11 +19,24 @@ #include <console/console.h> #include <elog.h> #include <intelblocks/pmclib.h> +#include <soc/intel/common/elog_xhci.h> #include <soc/pm.h> #include <soc/pci_devs.h> #include <soc/smbus.h> #include <stdint.h>
+#define XHCI_USB2_PORT_STATUS_REG 0x480 +#define XHCI_USB3_PORT_STATUS_REG 0x510 +#define XHCI_USB2_PORT_NUM 9 +#define XHCI_USB3_PORT_NUM 7 + +static struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { int i; @@ -54,6 +67,10 @@ if (ps->gpe0_sts[GPE0_A] & CSE_PME_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
+ /* XHCI */ + if (ps->gpe0_sts[GPE0_A] & XHCI_PME_STS) + pch_xhci_update_wake_event(PCH_DEV_XHCI, &usb_info); + /* SMBUS Wake */ if (ps->gpe0_sts[GPE0_A] & SMB_WAK_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32000 )
Change subject: soc/intel/apollolake: Add support to log XHCI wake events ......................................................................
Patch Set 1:
(3 comments)
https://review.coreboot.org/#/c/32000/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32000/1//COMMIT_MSG@16 PS1, Line 16: S0ix Enter Works with S3 too?
https://review.coreboot.org/#/c/32000/1/src/soc/intel/apollolake/elog.c File src/soc/intel/apollolake/elog.c:
https://review.coreboot.org/#/c/32000/1/src/soc/intel/apollolake/elog.c@28 PS1, Line 28: #define XHCI_USB2_PORT_STATUS_REG 0x480 : #define XHCI_USB3_PORT_STATUS_REG 0x510 : #define XHCI_USB2_PORT_NUM 9 : #define XHCI_USB3_PORT_NUM 7 Are these true for both APL and GLK?
https://review.coreboot.org/#/c/32000/1/src/soc/intel/apollolake/elog.c@33 PS1, Line 33: static struct xhci_usb_info usb_info = { const
Hello Aaron Durbin, Patrick Rudolph, Karthikeyan Ramasubramanian, Rajat Jain, Justin TerAvest, Shelley Chen, build bot (Jenkins), Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32000
to look at the new patch set (#2).
Change subject: soc/intel/apollolake: Add support to log XHCI wake events ......................................................................
soc/intel/apollolake: Add support to log XHCI wake events
Add support to identify and log the XHCI wake events for apollolake into event logs.
BUG=b:123429132 BRANCH=None TEST=Ensure that the system boots to ChromeOS. Ensure that the wake up events due to USB are logged into the event logs. 6 | 2019-03-21 09:22:18 | S0ix Enter 7 | 2019-03-21 09:22:22 | S0ix Exit 8 | 2019-03-21 09:22:22 | Wake Source | PME - XHCI (USB 2.0 port) | 9 9 | 2019-03-21 09:22:22 | Wake Source | GPE # | 13 10 | 2019-03-21 09:23:20 | ACPI Enter | S3 11 | 2019-03-21 09:23:30 | Wake Source | PME - XHCI (USB 2.0 port) | 9 12 | 2019-03-21 09:23:30 | ACPI Wake | S3 13 | 2019-03-21 09:23:30 | Wake Source | GPE # | 13
Change-Id: I55b850646dda8acaa086a9012c2d8b611016f932 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/elog.c 2 files changed, 23 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/32000/2
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32000 )
Change subject: soc/intel/apollolake: Add support to log XHCI wake events ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/#/c/32000/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/32000/1//COMMIT_MSG@16 PS1, Line 16: S0ix Enter
Works with S3 too?
Yes, checked it and updated the test logs here.
https://review.coreboot.org/#/c/32000/1/src/soc/intel/apollolake/elog.c File src/soc/intel/apollolake/elog.c:
https://review.coreboot.org/#/c/32000/1/src/soc/intel/apollolake/elog.c@28 PS1, Line 28: #define XHCI_USB2_PORT_STATUS_REG 0x480 : #define XHCI_USB3_PORT_STATUS_REG 0x510 : #define XHCI_USB2_PORT_NUM 9 : #define XHCI_USB3_PORT_NUM 7
Are these true for both APL and GLK?
GLK has one additional USB2 port compared to APL. Updated the code accordingly here.
https://review.coreboot.org/#/c/32000/1/src/soc/intel/apollolake/elog.c@33 PS1, Line 33: static struct xhci_usb_info usb_info = {
const
Done
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32000 )
Change subject: soc/intel/apollolake: Add support to log XHCI wake events ......................................................................
Patch Set 4: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32000 )
Change subject: soc/intel/apollolake: Add support to log XHCI wake events ......................................................................
soc/intel/apollolake: Add support to log XHCI wake events
Add support to identify and log the XHCI wake events for apollolake into event logs.
BUG=b:123429132 BRANCH=None TEST=Ensure that the system boots to ChromeOS. Ensure that the wake up events due to USB are logged into the event logs. 6 | 2019-03-21 09:22:18 | S0ix Enter 7 | 2019-03-21 09:22:22 | S0ix Exit 8 | 2019-03-21 09:22:22 | Wake Source | PME - XHCI (USB 2.0 port) | 9 9 | 2019-03-21 09:22:22 | Wake Source | GPE # | 13 10 | 2019-03-21 09:23:20 | ACPI Enter | S3 11 | 2019-03-21 09:23:30 | Wake Source | PME - XHCI (USB 2.0 port) | 9 12 | 2019-03-21 09:23:30 | ACPI Wake | S3 13 | 2019-03-21 09:23:30 | Wake Source | GPE # | 13
Change-Id: I55b850646dda8acaa086a9012c2d8b611016f932 Signed-off-by: Karthikeyan Ramasubramanian kramasub@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32000 Reviewed-by: Furquan Shaikh furquan@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/elog.c 2 files changed, 23 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 19cd296..d715f39 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -94,6 +94,7 @@ select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_XDCI select SOC_INTEL_COMMON_BLOCK_XHCI + select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_CSE diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index b03d5e6..c138b34 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -19,11 +19,29 @@ #include <console/console.h> #include <elog.h> #include <intelblocks/pmclib.h> +#include <intelblocks/xhci.h> #include <soc/pm.h> #include <soc/pci_devs.h> #include <soc/smbus.h> #include <stdint.h>
+#define XHCI_USB2_PORT_STATUS_REG 0x480 +#if CONFIG(SOC_INTEL_GLK) +#define XHCI_USB3_PORT_STATUS_REG 0x510 +#define XHCI_USB2_PORT_NUM 9 +#else +#define XHCI_USB3_PORT_STATUS_REG 0x500 +#define XHCI_USB2_PORT_NUM 8 +#endif +#define XHCI_USB3_PORT_NUM 7 + +static const struct xhci_usb_info usb_info = { + .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, + .num_usb2_ports = XHCI_USB2_PORT_NUM, + .usb3_port_status_reg = XHCI_USB3_PORT_STATUS_REG, + .num_usb3_ports = XHCI_USB3_PORT_NUM, +}; + static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { int i; @@ -54,6 +72,10 @@ if (ps->gpe0_sts[GPE0_A] & CSE_PME_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
+ /* XHCI */ + if (ps->gpe0_sts[GPE0_A] & XHCI_PME_STS) + pch_xhci_update_wake_event(&usb_info); + /* SMBUS Wake */ if (ps->gpe0_sts[GPE0_A] & SMB_WAK_STS) elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);
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Furquan Shaikh (Code Review) -
Karthik Ramasubramanian (Code Review)
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Patrick Georgi (Code Review)