Hello Shreesh Chhabbi,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/47983
to review the following change.
Change subject: soc/common: Program SF Mask MSRs for eNEM ......................................................................
soc/common: Program SF Mask MSRs for eNEM
Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.corp-partner.google.com Change-Id: I5781008a1447813317878a722cb894edcd6df946 --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig 8 files changed, 36 insertions(+), 30 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47983/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index f427340..06f8c2e 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -315,7 +315,7 @@ config USE_CANNONLAKE_CAR_NEM_ENHANCED bool "Enhanced Non-evict mode" select SOC_INTEL_COMMON_BLOCK_CAR - select USE_CAR_NEM_ENHANCED_V1 + select INTEL_CAR_NEM_ENHANCED help A current limitation of NEM (Non-Evict mode) is that code and data sizes are derived from the requirement to not write out any modified diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 9023b58..e66b0fb 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -51,21 +51,6 @@ ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced.
-config USE_CAR_NEM_ENHANCED_V1 - bool - select INTEL_CAR_NEM_ENHANCED - help - This config supports INTEL_CAR_NEM_ENHANCED mode on - SKL, KBL, CNL, WHL, CML and ICL and JSL platforms. - -config USE_CAR_NEM_ENHANCED_V2 - bool - select INTEL_CAR_NEM_ENHANCED - select COS_MAPPED_TO_MSB - help - This config supports INTEL_CAR_NEM_ENHANCED mode on - TGL platform. - config COS_MAPPED_TO_MSB bool depends on INTEL_CAR_NEM_ENHANCED @@ -73,6 +58,14 @@ On TGL and JSL platform the class of service configuration is mapped to MSB of MSR IA32_PQR_ASSOC.
+config CAR_HAS_SF_MASKS + bool + depends on INTEL_CAR_NEM_ENHANCED + help + In the case of non-inclusive cache architecture Snoop Filter MSR + IA32_L3_SF_MASK_x programming is required along with the data ways. + This is applicable for TGL and beyond. + config USE_INTEL_FSP_MP_INIT bool "Perform MP Initialization by FSP" default n diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index 5af1fc6..600399c 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -403,8 +403,28 @@ set_eviction_mask: mov %ebx, %ecx /* back up the number of ways */ mov %eax, %ebx /* back up the non-eviction mask*/ + +#if CONFIG(CAR_HAS_SF_MASKS) /* * Set MSR 0xC91 IA32_L3_MASK_1 or MSR 0x1891 IA32_CR_SF_QOS_MASK_1 + * Program MSR 0x1891 IA32_CR_SF_QOS_MASK_1 with + * total number of LLC ways + */ + mov %ecx, %eax + movl $IA32_CR_SF_QOS_MASK_1, %ecx + xorl %edx, %edx + wrmsr + /* + * Program MSR 0x1892 IA32_CR_SF_QOS_MASK_2 with + * total number of LLC ways + */ + movl $IA32_CR_SF_QOS_MASK_2, %ecx + xorl %edx, %edx + wrmsr +#endif + + /* + * Program MSR 0xC91 IA32_L3_MASK_1 * This MSR contain one bit per each way of LLC * - If this bit is '0' - the way is protected from eviction * - If this bit is '1' - the way is not protected from eviction @@ -417,26 +437,18 @@
xor $~0, %eax /* invert 32 bits */ and %ecx, %eax -#if CONFIG(USE_CAR_NEM_ENHANCED_V1) movl $IA32_L3_MASK_1, %ecx -#elif CONFIG(USE_CAR_NEM_ENHANCED_V2) - movl $IA32_CR_SF_QOS_MASK_1, %ecx -#endif xorl %edx, %edx wrmsr
/* - * Set MSR 0xC92 IA32_L3_MASK_1 or MSR 0x1892 IA32_CR_SF_QOS_MASK_2 + * Program MSR 0xC92 IA32_L3_MASK_2 * This MSR contain one bit per each way of LLC * - If this bit is '0' - the way is protected from eviction * - If this bit is '1' - the way is not protected from eviction */ mov %ebx, %eax -#if CONFIG(USE_CAR_NEM_ENHANCED_V1) movl $IA32_L3_MASK_2, %ecx -#elif CONFIG(USE_CAR_NEM_ENHANCED_V2) - movl $IA32_CR_SF_QOS_MASK_2, %ecx -#endif xorl %edx, %edx wrmsr /* diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 4981205..4fe491f 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -170,7 +170,7 @@ config USE_DENVERTON_NS_CAR_NEM_ENHANCED bool "Enhanced Non-evict mode" select SOC_INTEL_COMMON_BLOCK_CAR - select USE_CAR_NEM_ENHANCED_V1 + select INTEL_CAR_NEM_ENHANCED help A current limitation of NEM (Non-Evict mode) is that code and data sizes are derived from the requirement to not write out any modified cache line. diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 52e9a74..fee52e6 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -23,6 +23,7 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE + select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC @@ -64,7 +65,6 @@ select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI - select USE_CAR_NEM_ENHANCED_V1
config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 294f19f8..0a15f05 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -23,6 +23,7 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE + select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC @@ -61,7 +62,6 @@ select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_202005_BINDING - select USE_CAR_NEM_ENHANCED_V1 select DISPLAY_FSP_VERSION_INFO select HECI_DISABLE_USING_SMM
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index ba3af84..731e033 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -32,6 +32,7 @@ select HAVE_FSP_LOGO_SUPPORT select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER + select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select HAVE_INTEL_FSP_REPO @@ -77,7 +78,6 @@ select TSC_SYNC_MFENCE select UDELAY_TSC select UDK_2015_BINDING - select USE_CAR_NEM_ENHANCED_V1
config FSP_HYPERTHREADING bool "Enable Hyper-Threading" diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index b97b92e..dd14ad2 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -23,7 +23,8 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE - select USE_CAR_NEM_ENHANCED_V1 if !INTEL_CAR_NEM + select INTEL_CAR_NEM_ENHANCED if !INTEL_CAR_NEM + select CAR_HAS_SF_MASKS if INTEL_CAR_NEM_ENHANCED select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
Hello build bot (Jenkins), Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph, Shreesh Chhabbi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47983
to look at the new patch set (#2).
Change subject: soc/common: Program SF Mask MSRs for eNEM ......................................................................
soc/common: Program SF Mask MSRs for eNEM
Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.corp-partner.google.com Change-Id: I5781008a1447813317878a722cb894edcd6df946 --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig 8 files changed, 37 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47983/2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47983 )
Change subject: soc/common: Program SF Mask MSRs for eNEM ......................................................................
Patch Set 2:
(3 comments)
https://review.coreboot.org/c/coreboot/+/47983/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47983/2//COMMIT_MSG@8 PS2, Line 8: Can you please add a brief description of why the change is being made.
Also, BUG=b:???
https://review.coreboot.org/c/coreboot/+/47983/2/src/soc/intel/common/block/... File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/47983/2/src/soc/intel/common/block/... PS2, Line 412: mov %ecx, %eax This doesn't look right. It is writing # of LLC ways to the mask. But, you need to set all the bits in MASK_1 to 1.
https://review.coreboot.org/c/coreboot/+/47983/2/src/soc/intel/common/block/... PS2, Line 418: Program MSR 0x1892 IA32_CR_SF_QOS_MASK_2 with : * total number of LLC ways This doesn't match the recommendation. Is this intentional?
Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47983 )
Change subject: soc/common: Program SF Mask MSRs for eNEM ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47983/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47983/2//COMMIT_MSG@8 PS2, Line 8:
Can you please add a brief description of why the change is being made. […]
Hi Furquan, I was still updating the patch with details actually. I will complete it in few minutes.
Hello build bot (Jenkins), Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph, Shreesh Chhabbi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47983
to look at the new patch set (#3).
Change subject: soc/common: Program SF Mask MSRs for eNEM ......................................................................
soc/common: Program SF Mask MSRs for eNEM
Due to non-inclusive cache architecture in TGL, MSRs IA32_L3_SF_MASK_1 (1891h) and IA32_L3_SF_MASK_2 (1892h) need to be programmed. Recommendation is to set bits corresponding to all ways to 1b.
Bug=b:171601324 BRANCH=volteer Test=<Yet to run>
Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.corp-partner.google.com Change-Id: I5781008a1447813317878a722cb894edcd6df946 --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig 8 files changed, 37 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47983/3
Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47983 )
Change subject: soc/common: Program SF Mask MSRs for eNEM ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47983/2/src/soc/intel/common/block/... File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/47983/2/src/soc/intel/common/block/... PS2, Line 412: mov %ecx, %eax
This doesn't look right. It is writing # of LLC ways to the mask. […]
Furquan, if total number of LLC ways is 12, my understanding is only 12 LSB bits are to be set. Correct me if I am wrong.
Hello build bot (Jenkins), Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph, Shreesh Chhabbi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47983
to look at the new patch set (#4).
Change subject: soc/common: Program SF Mask MSRs for eNEM ......................................................................
soc/common: Program SF Mask MSRs for eNEM
Due to non-inclusive cache architecture in TGL, MSRs IA32_L3_SF_MASK_1 (1891h) and IA32_L3_SF_MASK_2 (1892h) need to be programmed. Recommendation is to set bits corresponding to available number of ways to 1b.
Bug=b:171601324 BRANCH=volteer Test=<Yet to run>
Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.corp-partner.google.com Change-Id: I5781008a1447813317878a722cb894edcd6df946 --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig 8 files changed, 37 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47983/4
Hello build bot (Jenkins), Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph, Shreesh Chhabbi,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47983
to look at the new patch set (#5).
Change subject: soc/common: Program SF Mask MSRs for eNEM ......................................................................
soc/common: Program SF Mask MSRs for eNEM
Due to non-inclusive cache architecture in TGL, MSRs IA32_L3_SF_MASK_1 (1891h) and IA32_L3_SF_MASK_2 (1892h) need to be programmed. Recommendation is to set bits corresponding to available number of ways to 1b.
Bug=b:171601324 BRANCH=volteer Test=<Yet to run>
Signed-off-by: Shreesh Chhabbi shreesh.chhabbi@intel.corp-partner.google.com Change-Id: I5781008a1447813317878a722cb894edcd6df946 --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig 8 files changed, 46 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47983/5
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47983 )
Change subject: soc/common: Program SF Mask MSRs for eNEM ......................................................................
Patch Set 5:
(5 comments)
https://review.coreboot.org/c/coreboot/+/47983/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47983/5//COMMIT_MSG@12 PS5, Line 12: corresponding to available number of ways to 1b. It would be helpful to also capture some information about why _V1/_V2 are being dropped. I am thinking it would be good to split this change into 2 CLs: 1. Drop _V2 and rename _V1 2. Add support for CAR_HAS_SF_MASKS
It is easier to see what is changing and why.
https://review.coreboot.org/c/coreboot/+/47983/5//COMMIT_MSG@16 PS5, Line 16: =<Yet to run> Needs update. Was this change verified?
https://review.coreboot.org/c/coreboot/+/47983/5/src/soc/intel/common/block/... File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/47983/5/src/soc/intel/common/block/... PS5, Line 413: %ecx ecx was used to back up the number of ways in line 404. Moving eax to ecx is going to overwrite that backup.
https://review.coreboot.org/c/coreboot/+/47983/5/src/soc/intel/common/block/... PS5, Line 415: $ %
https://review.coreboot.org/c/coreboot/+/47983/5/src/soc/intel/common/block/... PS5, Line 427: IA32_CR_SF_QOS_MASK_2 with : * total number of LLC ways The recommendation in the document Shyam shared was to set this to all 0s.
Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47983 )
Change subject: soc/common: Program SF Mask MSRs for eNEM ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47983/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47983/5//COMMIT_MSG@12 PS5, Line 12: corresponding to available number of ways to 1b.
It would be helpful to also capture some information about why _V1/_V2 are being dropped. […]
Hi Furquan, are you suggesting to use INTEL_CAR_NEM_ENHANCED_V1 instead of INTEL_CAR_NEM_ENHANCED in 1st patch after dividing the changes?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47983 )
Change subject: soc/common: Program SF Mask MSRs for eNEM ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47983/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47983/5//COMMIT_MSG@12 PS5, Line 12: corresponding to available number of ways to 1b.
Hi Furquan, are you suggesting to use INTEL_CAR_NEM_ENHANCED_V1 instead of INTEL_CAR_NEM_ENHANCED in […]
No, I meant:
Patch-1: Drop INTEL_CAR_NEM_ENHANCED_V2 and its associated code. Rename all occurrences of INTEL_CAR_NEM_ENHANCED_V1 with INTEL_CAR_NEM_ENHANCED.
Patch-2: Add support for CAR_HAS_SF_MASKS and its corresponding programming. Select CAR_HAS_SF_MASKS for TGL.
Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47983 )
Change subject: soc/common: Program SF Mask MSRs for eNEM ......................................................................
Patch Set 5:
(5 comments)
https://review.coreboot.org/c/coreboot/+/47983/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/47983/5//COMMIT_MSG@12 PS5, Line 12: corresponding to available number of ways to 1b.
No, I meant: […]
Ok got it. I will work on this change.
https://review.coreboot.org/c/coreboot/+/47983/5//COMMIT_MSG@16 PS5, Line 16: =<Yet to run>
Needs update. […]
It is not yet verified on SKU with 4MB L3 cache. So I had kept the field as it is and thought to get it tested on this SKU.
https://review.coreboot.org/c/coreboot/+/47983/5/src/soc/intel/common/block/... File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/47983/5/src/soc/intel/common/block/... PS5, Line 413: %ecx
ecx was used to back up the number of ways in line 404. […]
Yes. I can back it up in edx and restore back after SF Mask programming.
https://review.coreboot.org/c/coreboot/+/47983/5/src/soc/intel/common/block/... PS5, Line 415: $
%
Ack
https://review.coreboot.org/c/coreboot/+/47983/5/src/soc/intel/common/block/... PS5, Line 427: IA32_CR_SF_QOS_MASK_2 with : * total number of LLC ways
The recommendation in the document Shyam shared was to set this to all 0s.
Ok. I will update this.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47983 )
Change subject: soc/common: Program SF Mask MSRs for eNEM ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47983/5/src/soc/intel/common/block/... File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/47983/5/src/soc/intel/common/block/... PS5, Line 413: %ecx
Yes. I can back it up in edx and restore back after SF Mask programming.
what about using %edx directly? ``` mov %eax, %edx mov $0x01, %eax shl %dl, %eax subl $0x01, %eax ```
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47983 )
Change subject: soc/common: Program SF Mask MSRs for eNEM ......................................................................
Patch Set 5:
(2 comments)
https://review.coreboot.org/c/coreboot/+/47983/5/src/soc/intel/common/block/... File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/47983/5/src/soc/intel/common/block/... PS5, Line 413: %ecx
what about using %edx directly? […]
Yes, that should work.
https://review.coreboot.org/c/coreboot/+/47983/5/src/soc/intel/common/block/... PS5, Line 427: IA32_CR_SF_QOS_MASK_2 with : * total number of LLC ways
Ok. I will update this.
I had misremembered this. The document says "left to reset default". So, basically we don't need to configure this MSR at all.
Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47983 )
Change subject: soc/common: Program SF Mask MSRs for eNEM ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/47983/5/src/soc/intel/common/block/... File src/soc/intel/common/block/cpu/car/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/47983/5/src/soc/intel/common/block/... PS5, Line 413: %ecx
Yes, that should work.
Tim, that's great suggestion. I will change it.
Shreesh Chhabbi has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/47983 )
Change subject: soc/common: Program SF Mask MSRs for eNEM ......................................................................
Abandoned
It is now divided into 48284 & 48286.
-
Furquan Shaikh (Code Review) -
Shreesh Chhabbi (Code Review)
-
Tim Wawrzynczak (Code Review)