Change in coreboot[master]: Documentation: Add known bugs of x86_64 code on real hardware
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44733 )
Change subject: Documentation: Add known bugs of x86_64 code on real hardware ......................................................................
Documentation: Add known bugs of x86_64 code on real hardware
The bugs happen on real hardware or in qemu with KVM enabled. The very same code runs on some real devices and it runs in qemu with KVM disabled.
The bugs are so strange that no root cause could be found yet.
Change-Id: I01050f2e38f92c6b96e3258a5b619aa9ee685acc Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M Documentation/arch/x86/index.md 1 file changed, 15 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/44733/1
diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index 11d8a4f..a5406c0 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -65,3 +65,18 @@ * Test how well CAR works with x86_64 and paging * Improve mode switches * Test libgfxinit / VGA Option ROMs / FSP + +## Known bugs on real hardware + +The `x86_64` reference code runs fine in qemu and on some real x86 platforms. +However some issues have been observed and no workaround or explanation could +be found. It either works fine or not at all. Here's a list of known issues: + +* After entering long mode the FPU doesn't work any more, including accessing + MMX register. It works fine before entering long mode. +* Reading from virtual memory where the lower twelve address bits are zero + returns a fixed constant. Writing to that memory location has no effect. + Depeding on the variables stored in heap and stack and where the code + resides, undefined behaviour happens whenever the lower twelve bits are zero. +* Disabling paging in compability mode crashes the CPU. +* Returning from long mode to compability mode crashes the CPU.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44733 )
Change subject: Documentation: Add known bugs of x86_64 code on real hardware ......................................................................
Patch Set 1: Code-Review+1
(4 comments)
https://review.coreboot.org/c/coreboot/+/44733/1/Documentation/arch/x86/inde... File Documentation/arch/x86/index.md:
https://review.coreboot.org/c/coreboot/+/44733/1/Documentation/arch/x86/inde... PS1, Line 72: explanation Intel documents say that CAR operation has only been validated in flat 32-bit protected mode. It might be why there are problems, so I'd mention it as a note.
https://review.coreboot.org/c/coreboot/+/44733/1/Documentation/arch/x86/inde... PS1, Line 75: any more anymore
https://review.coreboot.org/c/coreboot/+/44733/1/Documentation/arch/x86/inde... PS1, Line 75: After entering long mode Add a comma after this:
After entering long mode, the FPU ...
https://review.coreboot.org/c/coreboot/+/44733/1/Documentation/arch/x86/inde... PS1, Line 76: register registers
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44733 )
Change subject: Documentation: Add known bugs of x86_64 code on real hardware ......................................................................
Patch Set 1:
(4 comments)
https://review.coreboot.org/c/coreboot/+/44733/1/Documentation/arch/x86/inde... File Documentation/arch/x86/index.md:
https://review.coreboot.org/c/coreboot/+/44733/1/Documentation/arch/x86/inde... PS1, Line 72: explanation
Intel documents say that CAR operation has only been validated in flat 32-bit protected mode. […]
Done
https://review.coreboot.org/c/coreboot/+/44733/1/Documentation/arch/x86/inde... PS1, Line 75: After entering long mode
Add a comma after this: […]
Done
https://review.coreboot.org/c/coreboot/+/44733/1/Documentation/arch/x86/inde... PS1, Line 75: any more
anymore
Done
https://review.coreboot.org/c/coreboot/+/44733/1/Documentation/arch/x86/inde... PS1, Line 76: register
registers
Done
Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44733
to look at the new patch set (#2).
Change subject: Documentation: Add known bugs of x86_64 code on real hardware ......................................................................
Documentation: Add known bugs of x86_64 code on real hardware
The bugs happen on real hardware or in qemu with KVM enabled. The very same code runs on some real devices and it runs in qemu with KVM disabled.
The bugs are so strange that no root cause could be found yet.
Change-Id: I01050f2e38f92c6b96e3258a5b619aa9ee685acc Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M Documentation/arch/x86/index.md 1 file changed, 17 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/44733/2
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44733 )
Change subject: Documentation: Add known bugs of x86_64 code on real hardware ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44733 )
Change subject: Documentation: Add known bugs of x86_64 code on real hardware ......................................................................
Patch Set 2: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44733 )
Change subject: Documentation: Add known bugs of x86_64 code on real hardware ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44733/2/Documentation/arch/x86/inde... File Documentation/arch/x86/index.md:
https://review.coreboot.org/c/coreboot/+/44733/2/Documentation/arch/x86/inde... PS2, Line 74: According to Intel Some contact or in some datasheet?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44733 )
Change subject: Documentation: Add known bugs of x86_64 code on real hardware ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44733/2/Documentation/arch/x86/inde... File Documentation/arch/x86/index.md:
https://review.coreboot.org/c/coreboot/+/44733/2/Documentation/arch/x86/inde... PS2, Line 74: According to Intel
Some contact or in some datasheet?
It's on non-public documentation.
Iru Cai (vimacs) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44733 )
Change subject: Documentation: Add known bugs of x86_64 code on real hardware ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/44733/2/Documentation/arch/x86/inde... File Documentation/arch/x86/index.md:
https://review.coreboot.org/c/coreboot/+/44733/2/Documentation/arch/x86/inde... PS2, Line 74: According to Intel x86_64 mode hasn't been validated in CAR environments. I think that's why MRC is in 32bit mode.
Hello build bot (Jenkins), Angel Pons, HAOUAS Elyes,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44733
to look at the new patch set (#3).
Change subject: Documentation: Add known bugs of x86_64 code on real hardware ......................................................................
Documentation: Add known bugs of x86_64 code on real hardware
The bugs happen on real hardware or in qemu with KVM enabled. The very same code runs on some real devices and it runs in qemu with KVM disabled.
The bugs are so strange that no root cause could be found yet.
Change-Id: I01050f2e38f92c6b96e3258a5b619aa9ee685acc Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M Documentation/arch/x86/index.md 1 file changed, 23 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/44733/3
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44733 )
Change subject: Documentation: Add known bugs of x86_64 code on real hardware ......................................................................
Patch Set 2:
(1 comment)
Added more test results to the strange memory bug.
https://review.coreboot.org/c/coreboot/+/44733/2/Documentation/arch/x86/inde... File Documentation/arch/x86/index.md:
https://review.coreboot.org/c/coreboot/+/44733/2/Documentation/arch/x86/inde... PS2, Line 74: According to Intel
It's on non-public documentation.
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44733 )
Change subject: Documentation: Add known bugs of x86_64 code on real hardware ......................................................................
Patch Set 3: Code-Review+2
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44733 )
Change subject: Documentation: Add known bugs of x86_64 code on real hardware ......................................................................
Patch Set 3:
(4 comments)
https://review.coreboot.org/c/coreboot/+/44733/3/Documentation/arch/x86/inde... File Documentation/arch/x86/index.md:
https://review.coreboot.org/c/coreboot/+/44733/3/Documentation/arch/x86/inde... PS3, Line 72: However nit: I'd add a comma after `However`
https://review.coreboot.org/c/coreboot/+/44733/3/Documentation/arch/x86/inde... PS3, Line 79: register nit: register*s*
https://review.coreboot.org/c/coreboot/+/44733/3/Documentation/arch/x86/inde... PS3, Line 86: don't doesn't
https://review.coreboot.org/c/coreboot/+/44733/3/Documentation/arch/x86/inde... PS3, Line 87: This in turn leads to undefined behaviour whenever the 'wrong' address is nit: remove the newline? having just two words on a single line feels weird
Hello build bot (Jenkins), Angel Pons,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/44733
to look at the new patch set (#4).
Change subject: Documentation: Add known bugs of x86_64 code on real hardware ......................................................................
Documentation: Add known bugs of x86_64 code on real hardware
The bugs happen on real hardware or in qemu with KVM enabled. The very same code runs on some real devices and it runs in qemu with KVM disabled.
The bugs are so strange that no root cause could be found yet.
Change-Id: I01050f2e38f92c6b96e3258a5b619aa9ee685acc Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M Documentation/arch/x86/index.md 1 file changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/44733/4
Attention is currently required from: Angel Pons. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44733 )
Change subject: Documentation: Add known bugs of x86_64 code on real hardware ......................................................................
Patch Set 4:
(4 comments)
File Documentation/arch/x86/index.md:
https://review.coreboot.org/c/coreboot/+/44733/comment/f56ae8a7_385b5f62 PS3, Line 72: However
nit: I'd add a comma after `However`
Done
https://review.coreboot.org/c/coreboot/+/44733/comment/f18a767c_b6c49717 PS3, Line 79: register
nit: register*s*
Done
https://review.coreboot.org/c/coreboot/+/44733/comment/ad6ba1b2_1ffeb4f3 PS3, Line 86: don't
doesn't
Done
https://review.coreboot.org/c/coreboot/+/44733/comment/6e3099bb_f616054d PS3, Line 87: This in turn leads to undefined behaviour whenever the 'wrong' address is
nit: remove the newline? having just two words on a single line feels weird
Done
Attention is currently required from: Patrick Rudolph. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44733 )
Change subject: Documentation: Add known bugs of x86_64 code on real hardware ......................................................................
Patch Set 4: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44733 )
Change subject: Documentation: Add known bugs of x86_64 code on real hardware ......................................................................
Documentation: Add known bugs of x86_64 code on real hardware
The bugs happen on real hardware or in qemu with KVM enabled. The very same code runs on some real devices and it runs in qemu with KVM disabled.
The bugs are so strange that no root cause could be found yet.
Change-Id: I01050f2e38f92c6b96e3258a5b619aa9ee685acc Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/44733 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Angel Pons th3fanbus@gmail.com --- M Documentation/arch/x86/index.md 1 file changed, 30 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved
diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index d22d31d..0e14115 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -65,3 +65,33 @@ * Test how well CAR works with x86_64 and paging * Improve mode switches * Test libgfxinit / VGA Option ROMs / FSP + +## Known bugs on real hardware + +According to Intel x86_64 mode hasn't been validated in CAR environments. +Until now it could be verified on various Intel platforms and no issues have +been found. + +## Known bugs on KVM enabled qemu + +The `x86_64` reference code runs fine in qemu soft-cpu, but has serious issues +when using KVM mode on some machines. The workaround is to *not* place +page-tables in ROM, as done in +[CB:49228](https://review.coreboot.org/c/coreboot/+/49228). + +Here's a list of known issues: + +* After entering long mode, the FPU doesn't work anymore, including accessing + MMX registers. It works fine before entering long mode. It works fine when + switching back to protected mode. Other registers, like SSE registers, are + working fine. +* Reading from virtual memory, when the page tables are stored in ROM, causes + the MMU to abort the "page table walking" mechanism when the lower address + bits of the virtual address to be translated have a specific pattern. + Instead of loading the correct physical page, the one containing the + page tables in ROM will be loaded and used, which breaks code and data as + the page table doesn't contain the expected data. This in turn leads to + undefined behaviour whenever the 'wrong' address is being read. +* Disabling paging in compability mode crashes the CPU. +* Returning from long mode to compability mode crashes the CPU. +* Entering long mode crashes on AMD host platforms.
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Angel Pons (Code Review) -
HAOUAS Elyes (Code Review)
-
Iru Cai (vimacs) (Code Review)
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Patrick Georgi (Code Review)
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Patrick Rudolph (Code Review)
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Paul Menzel (Code Review)