John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44003 )
Change subject: mb/intel/tglrvp: Update TCSS D3Hot and D3Cold configuration ......................................................................
mb/intel/tglrvp: Update TCSS D3Hot and D3Cold configuration
It is expected both of TCSS D3Hot and D3Cold are enabled by default.
BUG=None TEST=Verified both of TCSS D3Hot and D3Cold configuration on TGLRVP.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: Id569d8191f82f12379b57a9c50aec31776220bb5 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 0 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/44003/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index b4a121a..c2940e9 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -117,10 +117,6 @@ # Enable S0ix register "s0ix_enable" = "1"
- # D3Hot and D3Cold for TCSS - register "TcssD3HotEnable" = "1" - register "TcssD3ColdEnable" = "1" - #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index b08cd3c..5e6552b 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -113,10 +113,6 @@ # Enable S0ix register "s0ix_enable" = "1"
- # D3Hot and D3Cold for TCSS - register "TcssD3HotEnable" = "1" - register "TcssD3ColdEnable" = "1" - #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0"
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44003 )
Change subject: mb/intel/tglrvp: Update TCSS D3Hot and D3Cold configuration ......................................................................
Patch Set 1: Code-Review+1
Divya S Sasidharan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44003 )
Change subject: mb/intel/tglrvp: Update TCSS D3Hot and D3Cold configuration ......................................................................
Patch Set 1: Code-Review+1
Ravishankar Sarawadi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44003 )
Change subject: mb/intel/tglrvp: Update TCSS D3Hot and D3Cold configuration ......................................................................
Patch Set 1: Code-Review+2
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44003 )
Change subject: mb/intel/tglrvp: Update TCSS D3Hot and D3Cold configuration ......................................................................
Patch Set 1: Code-Review+2
Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44003 )
Change subject: mb/intel/tglrvp: Update TCSS D3Hot and D3Cold configuration ......................................................................
mb/intel/tglrvp: Update TCSS D3Hot and D3Cold configuration
It is expected both of TCSS D3Hot and D3Cold are enabled by default.
BUG=None TEST=Verified both of TCSS D3Hot and D3Cold configuration on TGLRVP.
Signed-off-by: John Zhao john.zhao@intel.com Change-Id: Id569d8191f82f12379b57a9c50aec31776220bb5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44003 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Caveh Jalali caveh@chromium.org Reviewed-by: Divya S Sasidharan divya.s.sasidharan@intel.com Reviewed-by: Ravishankar Sarawadi ravishankar.sarawadi@intel.com Reviewed-by: Wonkyu Kim wonkyu.kim@intel.com --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb M src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb 2 files changed, 0 insertions(+), 8 deletions(-)
Approvals: build bot (Jenkins): Verified Ravishankar Sarawadi: Looks good to me, approved Divya S Sasidharan: Looks good to me, but someone else must approve Caveh Jalali: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, approved
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index e8dc7bd..85f9e51 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -117,10 +117,6 @@ # Enable S0ix register "s0ix_enable" = "1"
- # D3Hot and D3Cold for TCSS - register "TcssD3HotEnable" = "1" - register "TcssD3ColdEnable" = "1" - #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index ef8de3c..5c275b3 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -113,10 +113,6 @@ # Enable S0ix register "s0ix_enable" = "1"
- # D3Hot and D3Cold for TCSS - register "TcssD3HotEnable" = "1" - register "TcssD3ColdEnable" = "1" - #HD Audio register "PchHdaDspEnable" = "1" register "PchHdaAudioLinkHdaEnable" = "0"
-
Caveh Jalali (Code Review) -
Divya S Sasidharan (Code Review)
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John Zhao (Code Review)
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Nick Vaccaro (Code Review)
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Ravishankar Sarawadi (Code Review)
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Wonkyu Kim (Code Review)