[S] Change in coreboot[master]: mb/system76/adl-p: Enable AER on CPU PCIe RP

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71662 )

Change subject: mb/system76/adl-p: Enable AER on CPU PCIe RP
......................................................................

mb/system76/adl-p: Enable AER on CPU PCIe RP

Tested with the following drives:

- Crucial P5 Plus (CT500P5PSSD8)
- Kingston KC3000 (SKC3000S/512G)
- Sabrent Rocket NVMe 4.0 (SB-ROCKET-NVMEe4-500)
- Samsung 970 EVO (MZ-V7E250)
- Samsung 970 EVO Plus (MZ-V7S250)
- Samsung 980 PRO (MZ-V8P2T0)
- WD Black SN850X (WDS100T2XD0E)
- WD Blue SN580 (WDS500G2B0C)
- WD Green SN350 (WDS240G2G0C)

Test:

- Drive is functional and has no unrecoverable errors on boot
- Drive is functional and has no unrecoverable errors after S0ix

Change-Id: I51492c97c48f760d4aa9e4a2b2e57b0f1a06d090
Signed-off-by: Tim Crawford 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71662
Tested-by: build bot (Jenkins) 
Reviewed-by: Jeremy Soller 
---
M src/mainboard/system76/adl-p/variants/darp8/overridetree.cb
M src/mainboard/system76/adl-p/variants/galp6/overridetree.cb
2 files changed, 32 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Jeremy Soller: Looks good to me, approved

diff --git a/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb b/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb
index 4caed3a..5f82c44 100644
--- a/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb
+++ b/src/mainboard/system76/adl-p/variants/darp8/overridetree.cb
@@ -20,7 +20,7 @@
    		register "cpu_pcie_rp[CPU_RP(1)]" = "{
    			.clk_src = 0,
    			.clk_req = 0,
-				.flags = PCIE_RP_LTR,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
    		}"
    		chip soc/intel/common/block/pcie/rtd3
    			register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_EN
diff --git a/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb b/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb
index e63e185..c10e17a 100644
--- a/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb
+++ b/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb
@@ -18,7 +18,7 @@
    		register "cpu_pcie_rp[CPU_RP(1)]" = "{
    			.clk_src = 0,
    			.clk_req = 0,
-				.flags = PCIE_RP_LTR,
+				.flags = PCIE_RP_LTR | PCIE_RP_AER,
    		}"
    		chip soc/intel/common/block/pcie/rtd3
    			register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_EN