Cliff Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84297?usp=email )
Change subject: soc/intel/ptl: Add GPE1 defines ......................................................................
soc/intel/ptl: Add GPE1 defines
defines for GPE number for additional STD GPE0 in PTL defines for GPE number for GPE1 defines for GPE1 bits NOTE: All GEP1 bits are STD GPE bits.
BUG=362310295 TEST=This cannot be tested directly.
Signed-off-by: Cliff Huang cliff.huang@intel.com Change-Id: Iebf6f6d02b37cc9702e4ee07c1ec0017b6628836 --- M src/soc/intel/pantherlake/include/soc/gpe.h M src/soc/intel/pantherlake/include/soc/pm.h 2 files changed, 297 insertions(+), 78 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/84297/1
diff --git a/src/soc/intel/pantherlake/include/soc/gpe.h b/src/soc/intel/pantherlake/include/soc/gpe.h index eb9a8bff..d5fcf42 100644 --- a/src/soc/intel/pantherlake/include/soc/gpe.h +++ b/src/soc/intel/pantherlake/include/soc/gpe.h @@ -5,4 +5,80 @@
#include <intelpch/gpe.h>
+/* additional GPE_STD bits in PTL GPE0 block */ +/* 0x6C GPE0_STS_127_96; 0x7C GPE0_EN_127_96 */ +#define GPE0_FIA_DFLEX 96 /* 0x60 */ + +#define GPE0_THERM 100 /* 0x64 */ +#define GPE0_TC_PME_B0 101 /* 0x65 */ + +#define GPE0_ISH 104 /* 0x68 */ + +#define GPE0_ME_SCI 108 /* 0x6C */ + +#define GPE0_USB_CON_DSX 113 /* 0x71 */ + +#define GPE0_TCSS_SX_WAKE 115 /* 0x73 */ +#define GPE0_TC_PCI_EXP 118 /* 0x76 */ +#define GPE0_TC_HOT_PLUG 119 /* 0x77 */ +#define GPE0_OSSE_SCI 120 /* 0x78 */ + +#undef GPE_MAX +#define GPE_MAX GPE0_OSSE_SCI + +/* 0x10 GPE1_STS_31_0; 0x1C GPE1_EN_31_0 */ +#define GPE1_CNVI_BT_PME_B0 146 /* 0x92 */ +#define GPE1_TC_IOM_PME_B0 145 /* 0x91 */ +#define GPE1_TC_TBT1_PME_B0 144 /* 0x90 */ +#define GPE1_TC_TBT0_PME_B0 143 /* 0x8F */ +#define GPE1_LPSS_PME_B0 142 /* 0x8E */ +#define GPE1_CSE_PME_B0 141 /* 0x8D */ +#define GPE1_XDCI_PME_B0 140 /* 0x8C */ +#define GPE1_ACE_PME_B0 138 /* 0x8A */ +#define GPE1_XHCI_PME_B0 137 /* 0x89 */ +#define GPE1_SATA_PME_B0 136 /* 0x88 */ +#define GPE1_CSME_PME_B0 135 /* 0x87 */ +#define GPE1_GBE_PME_B0 134 /* 0x86 */ +#define GPE1_CNVI_PME_B0 133 /* 0x85 */ +#define GPE1_OSSE_PME_B0 132 /* 0x84 */ +#define GPE1_TBTLSX_PME_B0 129 /* 0x81 */ + +/* 0x14 GPE1_STS_63_32; 0x20 GPE1_EN_63_32 */ +#define GPE1_PG5_PMA0_HOT_PLUG_3 191 /* 0xBF */ +#define GPE1_PG5_PMA0_HOT_PLUG_2 190 /* 0xBE */ +#define GPE1_PG5_PMA0_HOT_PLUG_1 189 /* 0xBD */ +#define GPE1_PG5_PMA0_HOT_PLUG_0 188 /* 0xBC */ +#define GPE1_PG5_PMA1_HOT_PLUG_3 187 /* 0xBB */ +#define GPE1_PG5_PMA1_HOT_PLUG_2 186 /* 0xBA */ +#define GPE1_PG5_PMA1_HOT_PLUG_1 185 /* 0xB9 */ +#define GPE1_PG5_PMA1_HOT_PLUG_0 184 /* 0xB8 */ +#define GPE1_TC_TBT1_HOT_PLUG 173 /* 0xAD */ +#define GPE1_TC_TBT0_HOT_PLUG 172 /* 0xAC */ +#define GPE1_TC_PCIE3_HOT_PLUG 171 /* 0xAB */ +#define GPE1_TC_PCIE2_HOT_PLUG 170 /* 0xAA */ +#define GPE1_TC_PCIE1_HOT_PLUG 169 /* 0xA9 */ +#define GPE1_TC_PCIE0_HOT_PLUG 168 /* 0xA8 */ +#define GPE1_IOE_HOT_PLUG 167 /* 0xA7 */ +#define GPE1_SPB_HOT_PLUG 161 /* 0xA1 */ +#define GPE1_SPA_HOT_PLUG 160 /* 0xA0 */ + +/* 0x18 GPE1_STS_95_64; 0x24 GPE1_EN_95_64 */ +#define GPE1_PG5_PMA0_PCI_EXP_3 223 /* 0xDF */ +#define GPE1_PG5_PMA0_PCI_EXP_2 222 /* 0xDE */ +#define GPE1_PG5_PMA0_PCI_EXP_1 221 /* 0xDD */ +#define GPE1_PG5_PMA0_PCI_EXP_0 220 /* 0xDC */ +#define GPE1_PG5_PMA1_PCI_EXP_3 219 /* 0xDB */ +#define GPE1_PG5_PMA1_PCI_EXP_2 218 /* 0xDA */ +#define GPE1_PG5_PMA1_PCI_EXP_1 217 /* 0xD9 */ +#define GPE1_PG5_PMA1_PCI_EXP_0 216 /* 0xD8 */ +#define GPE1_TC_TBT1_PCI_EXP 205 /* 0xCD */ +#define GPE1_TC_TBT0_PCI_EXP 204 /* 0xCC */ +#define GPE1_TC_PCIE3_PCI_EXP 203 /* 0xCB */ +#define GPE1_TC_PCIE2_PCI_EXP 202 /* 0xCA */ +#define GPE1_TC_PCIE1_PCI_EXP 201 /* 0xC9 */ +#define GPE1_TC_PCIE0_PCI_EXP 200 /* 0xC8 */ +#define GPE1_IOE_PCI_EXP 199 /* 0xC7 */ +#define GPE1_SPB_PCI_EXP 193 /* 0xC1 */ +#define GPE1_SPA_PCI_EXP 192 /* 0xC0 */ + #endif /* _SOC_PANTHERLAKE_GPE_H_ */ diff --git a/src/soc/intel/pantherlake/include/soc/pm.h b/src/soc/intel/pantherlake/include/soc/pm.h index b8a86fc..99387e9 100644 --- a/src/soc/intel/pantherlake/include/soc/pm.h +++ b/src/soc/intel/pantherlake/include/soc/pm.h @@ -3,82 +3,88 @@ #ifndef _SOC_PANTHERLAKE_PM_H_ #define _SOC_PANTHERLAKE_PM_H_
-#define PM1_STS 0x00 -#define WAK_STS BIT(15) -#define PCIEXPWAK_STS BIT(14) -#define PRBTNOR_STS BIT(11) -#define RTC_STS BIT(10) -#define PWRBTN_STS BIT(8) -#define GBL_STS BIT(5) -#define BM_STS BIT(4) -#define TMROF_STS BIT(0) -#define PM1_EN 0x02 -#define PCIEXPWAK_DIS BIT(14) -#define RTC_EN BIT(10) -#define PWRBTN_EN BIT(8) -#define GBL_EN BIT(5) -#define TMROF_EN BIT(0) -#define PM1_CNT 0x04 -#define GBL_RLS BIT(2) -#define BM_RLD BIT(1) -#define SCI_EN BIT(0) -#define PM1_TMR 0x08 -#define SMI_EN 0x30 -#define XHCI_SMI_EN BIT(31) -#define ME_SMI_EN BIT(30) -#define ESPI_SMI_EN BIT(28) -#define GPIO_UNLOCK_SMI_EN BIT(27) -#define INTEL_USB2_EN BIT(18) -#define LEGACY_USB2_EN BIT(17) -#define PERIODIC_EN BIT(14) -#define TCO_SMI_EN BIT(13) -#define MCSMI_EN BIT(11) -#define BIOS_RLS BIT(7) -#define SWSMI_TMR_EN BIT(6) -#define APMC_EN BIT(5) -#define SLP_SMI_EN BIT(4) -#define LEGACY_USB_EN BIT(3) -#define BIOS_EN BIT(2) -#define EOS BIT(1) -#define GBL_SMI_EN BIT(0) -#define SMI_STS 0x34 -#define SMI_STS_BITS 32 -#define XHCI_SMI_STS_BIT 31 -#define ME_SMI_STS_BIT 30 -#define ESPI_SMI_STS_BIT 28 -#define GPIO_UNLOCK_SMI_STS_BIT 27 -#define SPI_SMI_STS_BIT 26 -#define SCC_SMI_STS_BIT 25 -#define MONITOR_STS_BIT 21 -#define PCI_EXP_SMI_STS_BIT 20 -#define SMBUS_SMI_STS_BIT 16 -#define SERIRQ_SMI_STS_BIT 15 -#define PERIODIC_STS_BIT 14 -#define TCO_STS_BIT 13 -#define DEVMON_STS_BIT 12 -#define MCSMI_STS_BIT 11 -#define GPIO_STS_BIT 10 -#define GPE0_STS_BIT 9 -#define PM1_STS_BIT 8 -#define SWSMI_TMR_STS_BIT 6 -#define APM_STS_BIT 5 -#define SMI_ON_SLP_EN_STS_BIT 4 -#define LEGACY_USB_STS_BIT 3 -#define BIOS_STS_BIT 2 -#define GPE_CNTL 0x42 -#define SWGPE_CTRL BIT(1) -#define DEVACT_STS 0x44 -#define PM2_CNT 0x50 +#define PM1_STS 0x00 +#define WAK_STS BIT(15) +#define PCIEXPWAK_STS BIT(14) +#define PRBTNOR_STS BIT(11) +#define RTC_STS BIT(10) +#define PWRBTN_STS BIT(8) +#define GBL_STS BIT(5) +#define BM_STS BIT(4) +#define TMROF_STS BIT(0) +#define PM1_EN 0x02 +#define PCIEXPWAK_DIS BIT(14) +#define RTC_EN BIT(10) +#define PWRBTN_EN BIT(8) +#define GBL_EN BIT(5) +#define TMROF_EN BIT(0) +#define PM1_CNT 0x04 +#define GBL_RLS BIT(2) +#define BM_RLD BIT(1) +#define SCI_EN BIT(0) +#define PM1_TMR 0x08 +#define SMI_EN 0x30 +#define XHCI_SMI_EN BIT(31) +#define ME_SMI_EN BIT(30) +#define ESPI_SMI_EN BIT(28) +#define GPIO_UNLOCK_SMI_EN BIT(27) +#define INTEL_USB2_EN BIT(18) +#define LEGACY_USB2_EN BIT(17) +#define PERIODIC_EN BIT(14) +#define TCO_SMI_EN BIT(13) +#define MCSMI_EN BIT(11) +#define BIOS_RLS BIT(7) +#define SWSMI_TMR_EN BIT(6) +#define APMC_EN BIT(5) +#define SLP_SMI_EN BIT(4) +#define LEGACY_USB_EN BIT(3) +#define BIOS_EN BIT(2) +#define EOS BIT(1) +#define GBL_SMI_EN BIT(0) +#define SMI_STS 0x34 +#define SMI_STS_BITS 32 +#define XHCI_SMI_STS_BIT 31 +#define ME_SMI_STS_BIT 30 +#define ESPI_SMI_STS_BIT 28 +#define GPIO_UNLOCK_SMI_STS_BIT 27 +#define SPI_SMI_STS_BIT 26 +#define SCC_SMI_STS_BIT 25 +#define MONITOR_STS_BIT 21 +#define PCI_EXP_SMI_STS_BIT 20 +#define SMBUS_SMI_STS_BIT 16 +#define SERIRQ_SMI_STS_BIT 15 +#define PERIODIC_STS_BIT 14 +#define TCO_STS_BIT 13 +#define DEVMON_STS_BIT 12 +#define MCSMI_STS_BIT 11 +#define GPIO_STS_BIT 10 +#define GPE0_STS_BIT 9 +#define PM1_STS_BIT 8 +#define SWSMI_TMR_STS_BIT 6 +#define APM_STS_BIT 5 +#define SMI_ON_SLP_EN_STS_BIT 4 +#define LEGACY_USB_STS_BIT 3 +#define BIOS_STS_BIT 2 +#define GPE_CNTL 0x42 +#define SWGPE_CTRL BIT(1) +#define DEVACT_STS 0x44 +#define PM2_CNT 0x50
-#define GPE0_REG_MAX 4 -#define GPE0_REG_SIZE 32 -#define GPE0_STS(x) (0x60 + ((x) * 4)) -#define GPE_31_0 0 /* 0x60/0x70 = GPE[31:0] */ -#define GPE_63_32 1 /* 0x64/0x74 = GPE[63:32] */ -#define GPE_95_64 2 /* 0x68/0x78 = GPE[95:64] */ -#define GPE_STD 3 /* 0x6c/0x7c = Standard GPE */ -#define GPE_STS_RSVD GPE_STD -#define WADT_STS BIT(18) +#define GPE0_REG_MAX 4 +#define GPE0_REG_SIZE 32 +#define GPE0_STS(x) (0x60 + ((x) * 4)) +#define GPE_31_0 0 /* 0x60/0x70 = GPE[31:0] */ +#define GPE_63_32 1 /* 0x64/0x74 = GPE[63:32] */ +#define GPE_95_64 2 /* 0x68/0x78 = GPE[95:64] */ +#define GPE_STD 3 /* 0x6c/0x7c = Standard GPE */ +#define GPE_STS_RSVD GPE_STD +#define OSSE_SCI_STS BIT(24) +#define TC_HOT_PLUG_STS BIT(23) +#define TC_PCI_EXP_STS BIT(22) +#define TCSS_SX_WAKE_STS BIT(19) +#define WADT_STS BIT(18) +#define USB_CON_DSX_STS BIT(17) +#define LANWAKE_STS BIT(16) #define GPIO_T2_STS BIT(15) #define ESPI_STS BIT(14) #define PME_B0_STS BIT(13) @@ -86,23 +92,156 @@ #define PME_STS BIT(11) #define BATLOW_STS BIT(10) #define PCI_EXP_STS BIT(9) +#define ISH_STS BIT(8) #define SMB_WAK_STS BIT(7) #define TCOSCI_STS BIT(6) +#define TC_PME_B0_STS BIT(5) +#define THERM_STS BIT(4) #define SWGPE_STS BIT(2) #define HOT_PLUG_STS BIT(1) -#define GPE0_EN(x) (0x70 + ((x) * 4)) +#define FIA_DFLEX_STS BIT(0) + +#define GPE0_EN(x) (0x70 + ((x) * 4)) +#define OSSE_SCI_EN BIT(24) +#define TC_HOT_PLUG_EN BIT(23) +#define TC_PCI_EXP_EN BIT(22) +#define TCSS_SX_WAKE_EN BIT(19) #define WADT_EN BIT(18) +#define USB_CON_DSX_EN BIT(17) +#define LANWAKE_EN BIT(16) #define GPIO_T2_EN BIT(15) #define ESPI_EN BIT(14) -#define PME_B0_EN_BIT 13 -#define PME_B0_EN BIT(PME_B0_EN_BIT) +#define PME_B0_EN BIT(13) #define ME_SCI_EN BIT(12) #define PME_EN BIT(11) #define BATLOW_EN BIT(10) #define PCI_EXP_EN BIT(9) +#define ISH_EN BIT(8) +/* + SMB_WAK_ENi: bit 7 is reserved + NOTE: For Intel PCH, the SMBus slave will always be enabled as a wake event. +*/ #define TCOSCI_EN BIT(6) +#define TC_PME_B0_EN BIT(5) +#define THERM_EN BIT(4) #define SWGPE_EN BIT(2) #define HOT_PLUG_EN BIT(1) +#define FIA_DFLEX_EN BIT(0) + +#define EN_BLOCK 3 + +#if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_HAVE_GPE1) +#define GPE1_REG_MAX 3 +#define GPE1_EN(x) (0x1c + ((x) * 4)) +#define GPE1_STS(x) (0x10 + ((x) * 4)) +#endif + +#define GPE1_REG_SIZE 32 + +/* 0x10 GPE1_STS_31_0 General Purpose Event 1 Status [31:0] */ +#define CNVI_BT_PME_B0_STS BIT(18) +#define TC_IOM_PME_B0_STS BIT(17) +#define TC_TBT1_PME_B0_STS BIT(16) +#define TC_TBT0_PME_B0_STS BIT(15) +#define LPSS_PME_B0_STS BIT(14) +#define CSE_PME_B0_STS BIT(13) +#define XDCI_PME_B0_STS BIT(12) +#define ACE_PME_B0_STS BIT(10) +#define XHCI_PME_B0_STS BIT(9) +#define SATA_PME_B0_STS BIT(8) +#define CSME_PME_B0_STS BIT(7) +#define GBE_PME_B0_STS BIT(6) +#define CNVI_PME_B0_STS BIT(5) +#define OSSE_PME_B0_STS BIT(4) +#define TBTLSX_PME_B0_STS BIT(1) +/* 0x14 GPE1_STS_63_32 General Purpose Event 1 Status [63:32] */ +#define PG5_PMA0_HOT_PLUG_STS_3 BIT(31) +#define PG5_PMA0_HOT_PLUG_STS_2 BIT(30) +#define PG5_PMA0_HOT_PLUG_STS_1 BIT(29) +#define PG5_PMA0_HOT_PLUG_STS_0 BIT(28) +#define PG5_PMA1_HOT_PLUG_STS_3 BIT(27) +#define PG5_PMA1_HOT_PLUG_STS_2 BIT(26) +#define PG5_PMA1_HOT_PLUG_STS_1 BIT(25) +#define PG5_PMA1_HOT_PLUG_STS_0 BIT(24) +#define TC_TBT1_HOT_PLUG_STS BIT(13) +#define TC_TBT0_HOT_PLUG_STS BIT(12) +#define TC_PCIE3_HOT_PLUG_STS BIT(11) +#define TC_PCIE2_HOT_PLUG_STS BIT(10) +#define TC_PCIE1_HOT_PLUG_STS BIT(9) +#define TC_PCIE0_HOT_PLUG_STS BIT(8) +#define IOE_HOT_PLUG_STS BIT(7) +#define SPB_HOT_PLUG_STS BIT(1) +#define SPA_HOT_PLUG_STS BIT(0) +/* 0x18 GPE1_STS_95_64 General Purpose Event 1 Status [63:32] */ +#define PG5_PMA0_PCI_EXP_STS_3 BIT(31) +#define PG5_PMA0_PCI_EXP_STS_2 BIT(30) +#define PG5_PMA0_PCI_EXP_STS_1 BIT(29) +#define PG5_PMA0_PCI_EXP_STS_0 BIT(28) +#define PG5_PMA1_PCI_EXP_STS_3 BIT(27) +#define PG5_PMA1_PCI_EXP_STS_2 BIT(26) +#define PG5_PMA1_PCI_EXP_STS_1 BIT(25) +#define PG5_PMA1_PCI_EXP_STS_0 BIT(24) +#define TC_TBT1_PCI_EXP_STS BIT(13) +#define TC_TBT0_PCI_EXP_STS BIT(12) +#define TC_PCIE3_PCI_EXP_STS BIT(11) +#define TC_PCIE2_PCI_EXP_STS BIT(10) +#define TC_PCIE1_PCI_EXP_STS BIT(9) +#define TC_PCIE0_PCI_EXP_STS BIT(8) +#define IOE_PCI_EXP_STS BIT(7) +#define SPB_PCI_EXP_STS BIT(1) +#define SPA_PCI_EXP_STS BIT(0) +/* 0x1C GPE1_EN_31_0 General Purpose Event 1 Enable [31:0] */ +#define CNVI_BT_PME_B0_EN BIT(18) +#define TC_IOM_PME_B0_EN BIT(17) +#define TC_TBT1_PME_B0_EN BIT(16) +#define TC_TBT0_PME_B0_EN BIT(15) +#define LPSS_PME_B0_EN BIT(14) +#define CSE_PME_B0_EN BIT(13) +#define XDCI_PME_B0_EN BIT(12) +#define ACE_PME_B0_EN BIT(10) +#define XHCI_PME_B0_EN BIT(9) +#define SATA_PME_B0_EN BIT(8) +#define CSME_PME_B0_EN BIT(7) +#define GBE_PME_B0_EN BIT(6) +#define CNVI_PME_B0_EN BIT(5) +#define OSSE_PME_B0_EN BIT(4) +#define TBTLSX_PME_B0_EN BIT(1) +/* 0x20 GPE1_EN_63_32 General Purpose Event 1 Enable [63:32] */ +#define PG5_PMA0_HOT_PLUG_EN_3 BIT(31) +#define PG5_PMA0_HOT_PLUG_EN_2 BIT(30) +#define PG5_PMA0_HOT_PLUG_EN_1 BIT(29) +#define PG5_PMA0_HOT_PLUG_EN_0 BIT(28) +#define PG5_PMA1_HOT_PLUG_EN_3 BIT(27) +#define PG5_PMA1_HOT_PLUG_EN_2 BIT(26) +#define PG5_PMA1_HOT_PLUG_EN_1 BIT(25) +#define PG5_PMA1_HOT_PLUG_EN_0 BIT(24) +#define TC_TBT1_HOT_PLUG_EN BIT(13) +#define TC_TBT0_HOT_PLUG_EN BIT(12) +#define TC_PCIE3_HOT_PLUG_EN BIT(11) +#define TC_PCIE2_HOT_PLUG_EN BIT(10) +#define TC_PCIE1_HOT_PLUG_EN BIT(9) +#define TC_PCIE0_HOT_PLUG_EN BIT(8) +#define IOE_HOT_PLUG_EN BIT(7) +#define SPB_HOT_PLUG_EN BIT(1) +#define SPA_HOT_PLUG_EN BIT(0) +/* 0x24 GPE1_EN_95_64 General Purpose Event 1 Enable [63:32] */ +#define PG5_PMA0_PCI_EXP_EN_3 BIT(31) +#define PG5_PMA0_PCI_EXP_EN_2 BIT(30) +#define PG5_PMA0_PCI_EXP_EN_1 BIT(29) +#define PG5_PMA0_PCI_EXP_EN_0 BIT(28) +#define PG5_PMA1_PCI_EXP_EN_3 BIT(27) +#define PG5_PMA1_PCI_EXP_EN_2 BIT(26) +#define PG5_PMA1_PCI_EXP_EN_1 BIT(25) +#define PG5_PMA1_PCI_EXP_EN_0 BIT(24) +#define TC_TBT1_PCI_EXP_EN BIT(13) +#define TC_TBT0_PCI_EXP_EN BIT(12) +#define TC_PCIE3_PCI_EXP_EN BIT(11) +#define TC_PCIE2_PCI_EXP_EN BIT(10) +#define TC_PCIE1_PCI_EXP_EN BIT(9) +#define TC_PCIE0_PCI_EXP_EN BIT(8) +#define IOE_PCI_EXP_EN BIT(7) +#define SPB_PCI_EXP_EN BIT(1) +#define SPA_PCI_EXP_EN BIT(0)
/* * Enable SMI generation: @@ -143,6 +282,10 @@ uint32_t gblrst_cause[2]; uint32_t hpr_cause0; uint32_t prev_sleep_state; +#if CONFIG(SOC_INTEL_COMMON_BLOCK_ACPI_GPE1) + uint32_t gpe1_sts[3]; + uint32_t gpe1_en[3]; +#endif } __packed;
/* Get base address PMC memory mapped registers. */
-
Cliff Huang (Code Review)