Attention is currently required from: Arthur Heymans, Felix Held.
Hello Arthur Heymans, Felix Held,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/75102
to review the following change.
Change subject: device/pci: Limit default domain memory window ......................................................................
device/pci: Limit default domain memory window
When the default pci_domain_read_resources() is used, keep 32-bit memory resources below the limit given by CONFIG_DOMAIN_RESOURCE_32BIT_LIMT. This serves as a workaround for missing/wrong reservations of chipset resources.
This will help to get more stable results from our own allocator, but is far from a complete solution. Indvi- dual platform ASL code also needs to be considered, so the OS won't assign conflicting resources.
Tested on QEMU/Q35 and Siemens/Chili w/ and w/o top- down allocation. Fixes EHCI w/ top-down in QEMU.
Change-Id: Iae0d888eebd0ec11a9d6f12975ae24dc32a80d8c Signed-off-by: Nico Huber nico.huber@secunet.com --- M src/device/Kconfig M src/device/pci_device.c M src/soc/intel/common/block/systemagent/Kconfig 3 files changed, 52 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/75102/1
diff --git a/src/device/Kconfig b/src/device/Kconfig index ef73c40..43f23c5 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -531,6 +531,15 @@
if PCI
+config DOMAIN_RESOURCE_32BIT_LIMIT + hex + default 0xfe000000 + help + When the default pci_domain_read_resources() is used, + keep 32-bit memory resources below this limit. This is + used as a workaround for missing/wrong reservations of + chipset resources that usually reside above this limit. + config NO_ECAM_MMCONF_SUPPORT bool default n diff --git a/src/device/pci_device.c b/src/device/pci_device.c index e600f34..96b7877 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -7,6 +7,7 @@
#include <acpi/acpi.h> #include <assert.h> +#include <cbmem.h> #include <device/pci_ops.h> #include <bootmode.h> #include <console/console.h> @@ -561,8 +562,22 @@ res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
- /* Initialize the system-wide memory resources constraints. */ + /* + * Initialize 32-bit memory resource constraints. + * + * There are often undeclared chipset resources in lower + * memory and memory the 4G barrier. Hence, only allow + * one big range from cbmem_top to the configured limit. + */ res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->base = (uintptr_t)cbmem_top(); + res->limit = CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT - 1; + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED; + + /* Initialize 64-bit memory resource constraints above 4G. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(2, 0)); + res->base = 4ULL * GiB; res->limit = (1ULL << cpu_phys_address_size()) - 1; res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; diff --git a/src/soc/intel/common/block/systemagent/Kconfig b/src/soc/intel/common/block/systemagent/Kconfig index d8c217f..4d14fc1 100644 --- a/src/soc/intel/common/block/systemagent/Kconfig +++ b/src/soc/intel/common/block/systemagent/Kconfig @@ -6,6 +6,9 @@
if SOC_INTEL_COMMON_BLOCK_SA
+config DOMAIN_RESOURCE_32BIT_LIMIT + default 0xe0000000 + config ECAM_MMCONF_BASE_ADDRESS default 0xe0000000